아날로그/디지털 변환 회로
    2.
    发明公开
    아날로그/디지털 변환 회로 有权
    模拟/数字转换电路

    公开(公告)号:KR1020100084875A

    公开(公告)日:2010-07-28

    申请号:KR1020090004245

    申请日:2009-01-19

    CPC classification number: H03M1/0646 H03M1/0682 H03M1/365

    Abstract: PURPOSE: By including the averaging circuit of the Mobius band form and reassigning a plurality of analog blocks it linear, the A/D converter can minimize error. CONSTITUTION: In the comparator array(22), each compares one reference voltage and analog data among a plurality of reference voltages. The comparator array comprises a plurality of comparators for outputting the logic signal based on the comparison result. The averaging circuit(23) comprises a plurality of metal routings for recompensing the offset generating from at least a part of logic signals. It is each other contiguous among both ends of the comparator array to one and the comparator in which the minimum standard voltage is inputted and the comparator in which the maximum reference voltage is inputted are arranged.

    Abstract translation: 目的:通过包含Mobius频带形式的平均电路,并将多个模拟块重新分配为线性,A / D转换器可以最小化误差。 构成:在比较器阵列(22)中,每个比较多个参考电压中的一个参考电压和模拟数据。 比较器阵列包括用于基于比较结果输出逻辑信号的多个比较器。 平均电路(23)包括用于从至少一部分逻辑信号重新补偿偏移生成的多个金属布线。 比较器阵列的两端彼此相邻,并且输入最小标准电压的比较器和输入最大参考电压的比较器。

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