-
公开(公告)号：KR1020080000205A
公开(公告)日：2008-01-02
申请号：KR1020060057802
申请日：2006-06-27
Applicant: 삼성전자주식회사
CPC classification number: G09G3/3677 , G02F1/136213 , G09G2300/0413 , G09G2300/0876 , G09G2310/0286 , G11C19/28 , H03K19/01735 , H03K19/01742
Abstract: A gate driving circuit and a display device having the same are provided to reduce ripples in a control electrode of a pull-up unit by enlarging the capacitance of a charge capacitor ten times more than the parasite capacitance of a pull-up transistor. A gate driving circuit includes shift registers cascaded plural stages. An m-stage(SRCm) includes pull-up and pull-down parts(210,220), and a charger(212). The pull-up part includes a first transistor, which receives a first clock signal through a drain electrode thereof and outputs the first clock signal as a gate signal in response to the signal of a first node controlled by a first input signal inputted to a gate electrode. The pull-down part includes a second transistor for discharging the gate signal in response to a second input signal, which is inputted to gate electrode. The charger includes a charge capacitor between gate and source electrodes of the first transistor. The capacitance of the charge capacitor is ten times more than the parasite capacitance between drain and gate electrodes of a pull-up transistor.
Abstract translation: 提供了栅极驱动电路和具有该栅极驱动电路的显示装置，以通过将电荷电容器的电容放大到上拉晶体管的寄生电容的十倍来减少上拉单元的控制电极中的波纹。 栅极驱动电路包括级联多级的移位寄存器。 m级（SRCm）包括上拉和下拉部件（210,220）和充电器（212）。 上拉部分包括第一晶体管，其通过其漏极接收第一时钟信号，并且响应于由输入到门的第一输入信号控制的第一节点的信号而将第一时钟信号作为门信号输出 电极。 下拉部分包括用于响应于输入到栅电极的第二输入信号而放电门信号的第二晶体管。 充电器包括在第一晶体管的栅极和源极之间的电荷电容器。 电荷电容器的电容是上拉晶体管的漏极和栅电极之间的寄生电容的十倍。
-
公开(公告)号：KR1020070021742A
公开(公告)日：2007-02-23
申请号：KR1020050076338
申请日：2005-08-19
Applicant: 삼성전자주식회사
IPC: G02F1/1345
CPC classification number: G02F1/133514 , G02F1/133512 , G02F1/1343 , G02F2001/133519
Abstract: 본 발명은 합착제와의 접합 불량을 방지할 수 있는 컬러필터 기판에 관한 것이다.
본 발명에 따른 칼라필터 기판은 박막트랜지스터기판과 합착제에 의해 합착되며, 상기 합착제와 중첩되는 다수개의 에지부를 가지며 상기 에지부가 요철형태로 기판 상에 형성된 공통전극을 구비하는 것을 특징으로 한다.-
公开(公告)号：KR1020060023393A
公开(公告)日：2006-03-14
申请号：KR1020040072221
申请日：2004-09-09
Applicant: 삼성전자주식회사
IPC: G02F1/1337
CPC classification number: G02F1/134336 , G02F1/133707
Abstract: 본 발명의 실시예에 따른 액정 표시 장치는 게이트 전극을 가지는 게이트선을 포함하는 게이트선, 게이트선을 덮는 게이트 절연막, 게이트 절연막 위에 형성되어 있는 반도체층, 반도체층 위에 형성되어 있으며 소스 전극을 가지는 데이터선, 게이트 전극 상부에서 소스 전극과 각각 대향하고 있는 드레인 전극, 데이터선 위에 형성되어 있는 보호막, 보호막 위에 형성되어 있으며, 드레인 전극과 전기적으로 연결되어 있고, 제1 절개부를 가지는 화소 전극을 포함하는 박막 트랜지스터 패널과 화소 전극의 제1 절개부와 일정한 간격으로 배치되어 있는 제2 절개부를 가지는 공통 전극이 형성되어 있는 공통 전극 패널을 가진다. 이때, 화소의 중앙에 위치하는 도메인 분할 수단으로 사용되는 제1 절개부는 데이터선과 평행한 도메인 분할 수단간의 간격에 대하여 적어도 1/2 이상의 길이를 가지며, 더욱 바람직하게는 1:1 이상의 길이를 가진다.
액정표시장치, 도메인분할수단, 응답속도, 텍스쳐-
公开(公告)号：KR100947538B1
公开(公告)日：2010-03-12
申请号：KR1020030042850
申请日：2003-06-27
Applicant: 삼성전자주식회사
IPC: G02F1/136
CPC classification number: H01L27/1288 , G02F1/13458 , G02F1/136227 , G02F2001/136236 , G02F2001/13625 , G03F7/70358 , H01L27/1214 , H01L29/4908 , H01L29/66765 , H01L29/78669
Abstract: To improve product yield, light is scanned on a layer on a substrate through a mask. A pattern is formed on the substrate by the exposure of the layer. The direction of scanning is substantially perpendicular to a longitudinal direction of the pattern. The capacitance difference due to coupling of the pattern to be formed and a conductive layer formed through an insulation layer is reduced. Thus, failures of a display device are reduced and the product yield is increased.
-
公开(公告)号：KR1020050026300A
公开(公告)日：2005-03-15
申请号：KR1020030063332
申请日：2003-09-09
Applicant: 삼성전자주식회사
IPC: G02F1/13
CPC classification number: G02F1/133351 , G02F1/1345
Abstract: A TFT(Thin Film Transistor) array panel and a display device are provided to enhance contact reliability in a short point by biasedly arranging the short point for electrically connecting a common electrode and a pixel electrode, adjacent to one of two sides defining a corner at which boundary lines of two array panels meet each other. A TFT display device includes a TFT array panel(100), an opposite array panel(100), and a plurality of short points(600). The TFT array panel includes a plurality of pixel electrodes. The opposite display array panel includes a plurality of common electrodes facing the pixel electrodes. A boundary line of two sides defining at least one corner in the opposite array panel meets a boundary line of the TFT array panel. Each of the short points contacts the common electrode to provide common voltage to the common electrode and is disposed between the TFT array panel and the opposite array panel. At least one short point close to the corner is biasedly disposed at one of the two sides.
Abstract translation: 提供TFT（薄膜晶体管）阵列面板和显示装置，以通过偏置地布置用于电连接公共电极和像素电极的短点来邻近限定角部的两个侧面之一来提高短路中的接触可靠性 两个阵列面板的边界线彼此相遇。 TFT显示装置包括TFT阵列面板（100），相对的阵列面板（100）和多个短路点（600）。 TFT阵列面板包括多个像素电极。 相对的显示阵列面板包括面向像素电极的多个公共电极。 限定相对阵列面板中的至少一个角的两边的边界线与TFT阵列面板的边界线相交。 每个短点接触公共电极以向公共电极提供公共电压，并且设置在TFT阵列面板和相对的阵列面板之间。 靠近角落的至少一个短点偏置地设置在两侧之一处。
-
Patent Agency Ranking
公开(公告)号：KR1020050001268A
公开(公告)日：2005-01-06
申请号：KR1020030042850
申请日：2003-06-27
Applicant: 삼성전자주식회사
IPC: G02F1/136
CPC classification number: H01L27/1288 , G02F1/13458 , G02F1/136227 , G02F2001/136236 , G02F2001/13625 , G03F7/70358 , H01L27/1214 , H01L29/4908 , H01L29/66765 , H01L29/78669
Abstract: PURPOSE: An exposing method is provided to reduce screen spot by reducing luminance change caused by change of coupling capacitance between a data line and a pixel electrode, thereby improving yield of the product. CONSTITUTION: An exposing method includes the steps of exposing light from an upper portion of a mask having a predetermined pattern by scanning in a predetermined direction and transferring the exposed pattern onto a layer formed on a substrate. In this method, the scanning direction of light is vertical to a longitudinal direction of the pattern to be formed. Particularly, the method is easily applicable to a pattern having capacitance difference due to coupling with a conductive pattern formed adjacent to one of lower and upper layers using an insulating layer. An example of the pattern includes a data line. It is preferable that the scanning direction of light is vertical to the longitudinal direction of the data line in case that exposure for the formation of a pixel electrode as a conductive pattern is performed after the insulating layer is formed on the data line. This method facilitates the formation of an LCD device having a substrate with a size of 17' or greater.
Abstract translation: 目的：提供一种曝光方法，通过减少由数据线和像素电极之间的耦合电容的变化引起的亮度变化来减少屏幕斑点，从而提高产品的产量。 构成：曝光方法包括以下步骤：通过沿预定方向进行扫描从具有预定图案的掩模的上部曝光光，并将曝光图案转印到形成在基板上的层上。 在该方法中，光的扫描方向垂直于要形成的图案的纵向方向。 特别地，该方法可以容易地应用于使用绝缘层与由与下层和上层之一相邻形成的导电图案的耦合而具有电容差的图案。 该图案的示例包括数据线。 在数据线上形成绝缘层之后，在进行用于形成作为导电图案的像素电极的曝光的情况下，光的扫描方向优选垂直于数据线的纵向方向。 该方法有助于形成具有尺寸为17'或更大的基板的LCD装置。
-
公开(公告)号：KR1020080049984A
公开(公告)日：2008-06-05
申请号：KR1020060120651
申请日：2006-12-01
Applicant: 삼성전자주식회사
IPC: G02F1/1343
CPC classification number: G02F1/1343 , G02F1/136286 , G02F1/1368 , G02F2201/123 , H01L29/786
Abstract: A TFT(Thin Film Transistor) array panel is provided to minimize collision of LC molecules by making strength of a field by a first sub pixel electrode bigger than strength of a field by a coupling electrode, thereby reducing texture caused by the LC collision and accordingly providing a high luminance LCD(Liquid Crystal Display). A gate line(121,129) is formed on a substrate, and has a gate electrode(124). A semiconductor(154) is overlapped with the gate electrode. A gate insulating layer is formed on the semiconductor. A drain electrode(175) is formed on the gate insulating layer, and overlapped with the semiconductor. A data line(171,179) is formed on the gate insulating layer, and overlapped with the semiconductor. The data line has a source electrode(173) facing the drain electrode. A coupling electrode(176) is formed on the gate insulating layer, and is separated from the drain electrode and the data line. A passivation layer is formed on the semiconductor. A pixel electrode(191) is formed on the passivation layer, and includes first and second sub pixel electrodes(191a1,191b). The first sub pixel electrode is connected with the drain electrode through a first contact hole(185). The second sub pixel electrode is separated from the first sub pixel electrode, and connected with the coupling electrode through a second contact hole(186). The first pixel electrode is overlapped with the coupling electrode.
Abstract translation: 提供TFT（薄膜晶体管）阵列面板，以通过由耦合电极使场强大于场强的第一子像素电极使场强强化来最小化LC分子，从而减少由LC碰撞引起的纹理 提供高亮度LCD（液晶显示器）。 栅极线（121,129）形成在衬底上，并具有栅电极（124）。 半导体（154）与栅电极重叠。 在半导体上形成栅极绝缘层。 在栅极绝缘层上形成漏电极（175），与半导体重叠。 数据线（171,179）形成在栅绝缘层上，与半导体重叠。 数据线具有面向漏电极的源电极（173）。 耦合电极（176）形成在栅极绝缘层上，并与漏电极和数据线分离。 在半导体上形成钝化层。 像素电极（191）形成在钝化层上，并且包括第一和第二子像素电极（191a1,191b）。 第一子像素电极通过第一接触孔（185）与漏电极连接。 第二子像素电极与第一子像素电极分离，并通过第二接触孔（186）与耦合电极连接。 第一像素电极与耦合电极重叠。
-
公开(公告)号：KR100825097B1
公开(公告)日：2008-04-25
申请号：KR1020020000756
申请日：2002-01-07
Applicant: 삼성전자주식회사
IPC: G02F1/1345
Abstract: 본 발명은 액정 표시 장치에 관한 것으로, 기생 용량을 줄여서 신호 왜곡을 줄이기 위하여, 상부 기판의 공통 전극 중 하부 기판의 수리선과 중첩하는 공통 전극 부분을 제거한다. 본 발명에 따른 액정 표시 장치는, 제1 기판 위에 게이트선 및 데이터선이 서로 절연되어 교차하고 있으며, 게이트선 및 데이터선이 교차하여 이루어지는 화소 영역이 다수개 배열되는 표시 영역이 있다. 제1 기판 위의 표시 영역의 외부에는 수리선이 데이터선과 교차하고 있다. 제1 기판에 마주보고 대향되어 있는 제2 기판 위에는 블랙 매트릭스가 형성되어 있고, 블랙 매트릭스 위에는 수리선과 중첩하는 부분에 형성되어 있는 개구 패턴을 가지는 공통 전극이 형성되어 있다.
공통 전극, 기생 용량, 수리선, 신호 왜곡, 개구 패턴Abstract translation: 本发明涉及液晶显示器，并且为了通过减小寄生电容来减小信号失真，去除了与上基板的公共电极中的下基板的修复线重叠的公共电极部分。 根据本发明的液晶显示装置具有显示区域，在该显示区域中布置栅极线和数据线彼此交叉而彼此绝缘并且栅极线和数据线彼此交叉的多个像素区域。 修复线穿过第一基板上的显示区域外部的数据线。 在与第一基板相对的第二基板上形成黑矩阵，并且在黑矩阵上形成具有在与修复线重叠的部分上形成的开口图案的公共电极。
-
公开(公告)号：KR1020080035834A
公开(公告)日：2008-04-24
申请号：KR1020060102388
申请日：2006-10-20
Applicant: 삼성전자주식회사
Inventor： 안순일
IPC: G02F1/1345
CPC classification number: G02F1/13452 , H05K1/147 , H05K1/189
Abstract: A display device is provided to improve image quality by improving a structure of a lead line of a flexible film complex. A display device comprises an insulating substrate(100) having a display area and plural flexible film complexes(200) attached along one side of the insulating substrate. The flexible film complex comprises a film main body(210), a driving chip(220) mounted on the film main body, and a lead line(230). The lead line is formed on the film main body and connected to the driving chip. The lead line comprises first and second lead lines(231,232). The first lead line is obliquely prolonged on one side of the insulating substrate. The second lead line has a first part(232a) parallel to the first lead line and a second part(232b) bent at the first part.
Abstract translation: 提供一种通过改进柔性膜复合体的引线的结构来提高图像质量的显示装置。 显示装置包括具有显示区域的绝缘基板（100）和沿绝缘基板的一侧附着的多个柔性膜复合体（200）。 柔性膜复合体包括膜主体（210），安装在膜主体上的驱动芯片（220）和引线（230）。 导线形成在胶片主体上并连接到驱动芯片。 引线包括第一引线和第二引线（231,232）。 第一引线在绝缘基板的一侧倾斜延伸。 第二引线具有平行于第一引线的第一部分（232a）和在第一部分弯曲的第二部分（232b）。
-
公开(公告)号：KR1020080020331A
公开(公告)日：2008-03-05
申请号：KR1020060083694
申请日：2006-08-31
Applicant: 삼성전자주식회사
IPC: G02F1/136
CPC classification number: G02F1/136286 , G02F1/13452 , G02F1/13458 , G02F1/1368 , G02F2202/22 , G09G2300/0413 , G09G2330/06
Abstract: A TFT substrate is provided to equip an electrostatic protection circuit with dummy signal lines for electrostatic protection and plural diodes to prevent inflow of static electricity, thereby reducing faults generated by the static electricity. A TFT(Thin Film Transistor) substrate comprises the followings. Plural first signal lines(330) receive vertical synchronization start signals, and plural second signal lines(370) receive storage signals. A gate driving circuit is connected to the first and second signal lines. Plural dummy signal lines(350) for electrostatic protection form capacitor by being overlapped with the first signal lines, and are connected with the second signal lines.
Abstract translation: 提供TFT基板，为静电保护电路配备用于静电保护的虚拟信号线和多个二极管，以防止静电的流入，从而减少由静电产生的故障。 TFT（薄膜晶体管）基板包括以下。 多个第一信号线（330）接收垂直同步起始信号，多个第二信号线（370）接收存储信号。 栅极驱动电路连接到第一和第二信号线。 用于静电保护的多个虚拟信号线（350）通过与第一信号线重叠而形成电容器，并与第二信号线连接。
-
-
-
-
-
-
-
-
-
Search Results
17
records
(took 0.016 seconds)
