公开(公告)号：KR1020080033614A

公开(公告)日：2008-04-17

申请号：KR1020060099301

申请日：2006-10-12

Applicant: 삼성전자주식회사

Inventor： 임민환 ,  이운경 ,  최정혁

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/76224 ,  H01L21/76838 ,  H01L27/11526

Abstract: A non volatile memory device and a method for fabricating the same are provided to prevent a trench side wall pitting by securing a process margin when forming a recess region, and to prevent deterioration of device property caused by a current leakage by keeping a predetermined interval between an activation region and a control gate. A device isolation layer(144) defines an active region and a field region of a semiconductor substrate, and includes a recess region having a predetermined depth. A floating gate(FG) comprises a first gate pattern(136) and a second gate pattern(152), and comprises at least one part which is wider than the width of the active region. The first gate pattern is located on the active region by inserting a tunnel insulating layer. The second gate pattern is located on a sidewall of the first gate pattern, and a lower part of the second gate pattern is located on the upper level than the lower part of the first gate pattern. A control gate(170) is located above the floating gate by inserting a dielectric layer.

Abstract translation: 提供一种非易失性存储器件及其制造方法，用于通过在形成凹陷区域时确保工艺余量来防止沟槽侧壁点蚀，并且通过保持预定的间隔来防止由电流泄漏引起的器件特性的劣化 激活区域和控制门。 器件隔离层（144）限定半导体衬底的有源区和场区，并且包括具有预定深度的凹陷区。 浮动栅极（FG）包括第一栅极图案（136）和第二栅极图案（152），并且包括比有源区域的宽度宽的至少一个部分。 通过插入隧道绝缘层，第一栅极图案位于有源区上。 第二栅极图案位于第一栅极图案的侧壁上，并且第二栅极图案的下部位于比第一栅极图案的下部更高的电平上。 控制栅极（170）通过插入电介质层位于浮动栅极上方。

公开(公告)号：KR1020030066052A

公开(公告)日：2003-08-09

申请号：KR1020020006206

申请日：2002-02-04

Applicant: 삼성전자주식회사

Inventor： 허창현 ,  엄중섭 ,  김경희 ,  전은성 ,  임민환

IPC: H01L21/3105

Abstract: PURPOSE: A method of forming an interlayer dielectric in a semiconductor memory device is provided to prevent fall-down of a metal line formed at the edge of a cell block by reducing step difference of an interlayer dielectric between a cell region and the nearest peripheral region. CONSTITUTION: A storage pole and a plate pole are formed on a cell region for semiconductor memory. A peripheral circuit is formed on a peripheral region. An interlayer dielectric(BPSG)(20) is deposited on the resultant structure. CMP is performed to planarize a portion of the interlayer dielectric in the cell region. A BPSG reflow process is carried out to densify the interlayer dielectric.

Abstract translation: 目的：提供一种在半导体存储器件中形成层间电介质的方法，用于通过减小电池区域和最近周边区域之间的层间电介质的步进差来防止形成在电池块边缘处的金属线的下降 。 构成：在半导体存储器的单元区域上形成存储极和极极。 周边电路形成在周边区域。 在所得结构上沉积层间电介质（BPSG）（20）。 执行CMP以平坦化单元区域中的层间电介质的一部分。 进行BPSG回流工艺以致密化层间电介质。

公开(公告)号：KR1020030066001A

公开(公告)日：2003-08-09

申请号：KR1020020006134

申请日：2002-02-04

Applicant: 삼성전자주식회사

Inventor： 엄중섭 ,  김경희 ,  임민환 ,  허창현

IPC: H01L21/28

Abstract: PURPOSE: A method of forming contact in a semiconductor device is provided to improve contact filling and reduce seam's size in contact plug formation, and prevent a damage of a lower conductive layer by blocking plasma or chemical permeating through seam in the contact plug formation. CONSTITUTION: A portion of an insulation layer(30) to be contact hole is etched and a lower conductive layer(10) is exposed to form a contact hole. The first barrier layer(51) is formed in the contact hole. The first plug layer(61) is formed on the first barrier layer. The second barrier layer(71) is on the resultant structure. The second plug layer(81) is on it.

Abstract translation: 目的：提供一种在半导体器件中形成接触的方法，以改善接触填充并减少接触插塞形成中的接缝尺寸，并通过阻止等离子体或化学物质渗透通过接触插塞结构中的接缝来防止下导电层的损坏。 构成：蚀刻作为接触孔的绝缘层（30）的一部分，并且露出下导电层（10）以形成接触孔。 第一阻挡层（51）形成在接触孔中。 第一插塞层（61）形成在第一阻挡层上。 第二阻挡层（71）在所得结构上。 第二插头层（81）在其上。

公开(公告)号：KR1020030044198A

公开(公告)日：2003-06-09

申请号：KR1020010074865

申请日：2001-11-29

Applicant: 삼성전자주식회사

Inventor： 임민환 ,  엄중섭 ,  김경희 ,  허창현 ,  전은성

IPC: H01L27/04

Abstract: PURPOSE: A method for fabricating a storage node of a capacitor of a memory device is provided to increase an align margin of an exposure process by reducing the thickness of a photoresist layer, and to prevent an electric leakage caused by partial damage by making the upper corner of a stack-type storage node in order to prevent concentration of stress on a dielectric layer stacked on the storage node. CONSTITUTION: A conductive layer for the storage node is formed. A photoresist pattern(253) is formed on the conductive layer wherein the thickness of 1000 angstrom of the photoresist pattern is left when the conductive layer is completely etched. An anisotropical etch process is performed on the conductive layer by using the photoresist pattern as an etch mask.

Abstract translation: 目的：提供一种用于制造存储器件的电容器的存储节点的方法，以通过减小光致抗蚀剂层的厚度来增加曝光处理的对准余量，并且通过使上部 以防止堆积在存储节点上的电介质层上的应力集中。 构成：形成用于存储节点的导电层。 在导电层上形成光致抗蚀剂图案（253），其中当导电层被完全蚀刻时留下光致抗蚀剂图案的厚度为1000埃。 通过使用光致抗蚀剂图案作为蚀刻掩模，在导电层上进行各向异性热蚀刻处理。

公开(公告)号：KR100366632B1

公开(公告)日：2003-01-09

申请号：KR1020000059459

申请日：2000-10-10

Applicant: 삼성전자주식회사

Inventor： 김성봉 ,  김주영 ,  임민환

IPC: H01L21/28

CPC classification number: H01L21/76843 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided in which a lower plug electrically connected with an active region of a wafer has a recession, and a conductive layer has a projection fitted into the recession of the lower plug, so that a contact area between the lower plug and the conductive layer increases without increasing a contact resistance therebetween. Thus, the conductive layer can endure physical impacts applied in the formation of the conductive layer itself and in subsequent integration processes, without detaching from the lower plug or the wafer.

Abstract translation: 提供了一种半导体器件及其制造方法，其中与晶片的有源区电连接的下插塞具有凹陷，并且导电层具有配合到下插塞的凹陷中的突起， 下插头与导电层之间的接触面积增大而不增加它们之间的接触电阻。 因此，导电层可以忍受在形成导电层本身和随后的整合过程中施加的物理冲击，而不会从下插塞或晶片脱离。

公开(公告)号：KR1020060083341A

公开(公告)日：2006-07-20

申请号：KR1020050003850

申请日：2005-01-14

Applicant: 삼성전자주식회사

Inventor： 임민환

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

Abstract: 비휘발성 메모리 장치의 제조 방법을 제공한다. 이 방법은 반도체기판 상에 제 1 부유 게이트 패턴들을 형성하고, 상기 제 1 부유 게이트 패턴들 상부에 돌기부들이 형성된 내측벽을 갖는 실린더형의 제 2 부유 게이트 패턴을 형성하고, 상기 돌기부들이 형성된 상기 제 2 부유 게이트 패턴의 내측벽을 덮는 게이트 층간절연막을 형성한 후, 상기 게이트 층간절연막 상에 제어 게이트막을 형성하는 단계를 포함한다.

公开(公告)号：KR1020020028446A

公开(公告)日：2002-04-17

申请号：KR1020000059459

申请日：2000-10-10

Applicant: 삼성전자주식회사

Inventor： 김성봉 ,  김주영 ,  임민환

IPC: H01L21/28

CPC classification number: H01L21/76843 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PURPOSE: A semiconductor device capable of controlling delamination of a conductive layer is provided to prevent the conductive layer from being delaminated from a lower plug or wafer even when a physical impact is applied in a process for forming the conductive layer or subsequent integration process, by making the lower plug electrically connected to an active region have a recess and by making the conductive layer connected to the lower plug include a protrusion corresponding to the recess. CONSTITUTION: The first interlayer dielectric(310) has an opening. A diffusion barrier layer(314a) comes in contact with the first interlayer dielectric, formed on a surface inside the opening. The lower plug(316a) has the recess, formed on the diffusion barrier layer inside the opening. The second interlayer dielectric has a groove exposing at least the recess, formed on the first interlayer dielectric. A glue layer(320) is formed on the surface of the groove and the recess. The conductive layer fills the groove and the recess, formed on the glue layer.

Abstract translation: 目的：提供一种能够控制导电层的分层的半导体器件，以防止导电层从下部插塞或晶片分层，即使在用于形成导电层的工艺或随后的整合工艺中施加物理冲击时，通过 使得与有源区域电连接的下插头具有凹部，并且通过使连接到下插塞的导电层包括对应于凹部的突起。 构成：第一层间电介质（310）具有开口。 扩散阻挡层（314a）与形成在开口内的表面上的第一层间电介质接触。 下塞（316a）具有形成在开口内的扩散阻挡层上的凹部。 第二层间电介质具有至少露出形成在第一层间电介质上的凹部的凹槽。 在凹槽和凹槽的表面上形成胶层（320）。 导电层填充形成在胶层上的凹槽和凹槽。