公开(公告)号：KR1020020042031A

公开(公告)日：2002-06-05

申请号：KR1020000071719

申请日：2000-11-29

Applicant: 삼성전자주식회사

Inventor： 이형용 ,  전석배

IPC: G11C29/00

Abstract: PURPOSE: A test mode setting circuit is provided to extend the number of test mode cases by two times, and easily detect a defectiveness of a memory device. CONSTITUTION: A test mode setting circuit includes a row signal, a MODSET signal, many address signals, a switch control circuit(500), and a test mode output part(550). The row signal is generated in a system so as to detect a defectiveness of a memory device. An MODSET signal is enabled by a write signal, a column signal and the row signal in order to defect a defective memory device. Many address signals transmit information for selecting one of many test modes to the switch control circuit(500). The switch control circuit(500) generates a frame signal and inverse frame signal in response to one of many address signals and the row signal. The test mode output part(550) receives the MODSET signal, many address signals, the frame signal and the inverse frame signal of the switch control circuit(500), and outputs many test mode signals.

Abstract translation: 目的：提供测试模式设置电路，将测试模式的数量扩展两次，并容易地检测存储设备的缺陷。 构成：测试模式设置电路包括行信号，MODSET信号，许多地址信号，开关控制电路（500）和测试模式输出部分（550）。 在系统中生成行信号，以便检测存储器件的缺陷。 通过写入信号，列信号和行信号使能MODSET信号，以便缺陷存储器件。 许多地址信号向开关控制电路（500）发送用于选择许多测试模式之一的信息。 开关控制电路（500）响应多个地址信号和行信号之一产生帧信号和反相帧信号。 测试模式输出部分（550）接收MODSET信号，许多地址信号，开关控制电路（500）的帧信号和反相帧信号，并输出许多测试模式信号。

公开(公告)号：KR1020020011213A

公开(公告)日：2002-02-08

申请号：KR1020000044578

申请日：2000-08-01

Applicant: 삼성전자주식회사

Inventor： 이형용 ,  전석배 ,  박충선

IPC: G11C29/00

CPC classification number: G11C29/02

Abstract: PURPOSE: A semiconductor memory device with a sense amp control circuit for detecting bit line failure and a control method therefor are provided to effectively detect a failure in a bit line bridge by differently setting sensing time at bit lines. CONSTITUTION: A RAS(row address strobe signal) delay(300) delays a row address strobe signal(/RAS) by a predetermined time and outputs a delayed RAS signal(D_RAS). A sense amp control signal generator(310) generates first and second sense amp control signals which are generated in response to the delayed RAS signal(D_RAS) and a predetermined test mode control signal and are enabled in same timing or different timings in accordance with the operational modes of the semiconductor memory device. First sense amps(320) sense and amplify the potential of (2N-1)th bit line pairs in response to the first sense amp control signal. Second sense amps(330) sense and amplify the potential of 2N-th bit line pairs in response to the second sense amp control signal.

Abstract translation: 目的：提供一种具有用于检测位线故障的检测放大器控制电路及其控制方法的半导体存储器件，以通过不同地设置位线处的感测时间来有效地检测位线桥中的故障。 构成：RAS（行地址选通信号）延迟（300）将行地址选通信号（RAS）延迟预定时间并输出延迟的RAS信号（D_RAS）。 感测放大器控制信号发生器（310）产生响应于延迟的RAS信号（D_RAS）产生的第一和第二读出放大器控制信号和预定的测试模式控制信号，并且在相同定时或不同的定时根据 半导体存储器件的工作模式。 响应于第一感测放大器控制信号，第一感测放大器（320）感测并放大（2N-1）位线对的电位。 响应于第二感测放大器控制信号，第二感测放大器（330）感测并放大第2N位线对的电位。

公开(公告)号：KR1020010090169A

公开(公告)日：2001-10-18

申请号：KR1020000014825

申请日：2000-03-23

Applicant: 삼성전자주식회사

Inventor： 이형용 ,  전석배 ,  박충선

IPC: G11C11/407

CPC classification number: G11C7/1039 ,  G11C7/106 ,  G11C11/4093

Abstract: PURPOSE: A pipeline of a semiconductor memory device outputting data bidirectionally is provided, which can judge whether a fail of output data is caused by the pipeline or the output data is originally defective when being input, when the output data is defective. CONSTITUTION: A semiconductor memory device(101) comprising a pipeline(111) comprises a memory bank(105), the first switching unit(121), the second switching unit(122), a data output circuit(131), and output buffer(141) and a pad(151). The first switching unit is connected to the first output terminal of the pipeline, and the second switching unit is connected to the second output terminal of the pipeline. Data stored in the memory bank during a read operation of the semiconductor memory device are transferred in parallel and stored in the pipeline. The data stored in the pipeline are transferred to the data output circuit serially through the first switching unit and the first output line(L1) by being synchronized to an output clock signal(OCLK) or are transferred to the second switching unit and the second output line(L2) by being synchronized to the output clock signal. The data transferred to the data output circuit are transferred to the output buffer, and the output buffer converts a voltage level of the data into a voltage level proper to an external system.

Abstract translation: 目的：提供双向输出数据的半导体存储器件的流水线，当输出数据有缺陷时，可以判断输出数据的故障是由管道引起的还是输入数据原本是有缺陷的。 构成：包括流水线（111）的半导体存储器件（101）包括存储体（105），第一切换单元（121），第二切换单元（122），数据输出电路（131）和输出缓冲器 （141）和垫（151）。 第一开关单元连接到管线的第一输出端子，第二开关单元连接到管道的第二输出端子。 在半导体存储器件的读取操作期间存储在存储体中的数据被并行传送并存储在管线中。 存储在流水线中的数据通过与输出时钟信号（OCLK）同步而通过第一开关单元和第一输出线（L1）串行地传送到数据输出电路，或者被传送到第二开关单元和第二输出 线（L2）通过与输出时钟信号同步。 传送到数据输出电路的数据被传送到输出缓冲器，输出缓冲器将数据的电压电平转换成适合外部系统的电压电平。

公开(公告)号：KR1020010019338A

公开(公告)日：2001-03-15

申请号：KR1019990035684

申请日：1999-08-26

Applicant: 삼성전자주식회사

Inventor： 전석배 ,  소병환

IPC: B25B11/00

Abstract: PURPOSE: A fixing device for a both-side processing wafer is provided to prevent damage of both sides of a wafer and vibration or bending of the wafer while easily turning over the wafer in the process of processing the both sides of the wafer. CONSTITUTION: A fixing device for a both-side processing wafer includes upper and lower guard rings(22,24) for grasping an edge part of a wafer(10) at upper and lower parts in a circumferential direction, either of the upper and lower guard rings being hinge-coupled rotatably for separating the wafer, fixing elements(42,44) for integrally fixing the upper and lower guard rings, rotation shafts(52,54) fixed for reversing the upper and lower guard rings while grasping the wafer by an outer surface of the fixing element, a fixing chuck(60) formed with an insertion groove(62) for inserting an end of the respective fixing elements, and conveying elements for fixing and conveying the wafer without damaging both sides of the wafer.

Abstract translation: 目的：提供一种用于双面处理晶片的定影装置，以在晶片的两侧的处理过程中容易地翻转晶片，以防止晶片两侧的损坏和晶片的振动或弯曲。 构成：用于双面处理晶片的固定装置包括上和下保护环（22,24），用于在圆周方向上夹持上部和下部的晶片（10）的边缘部分，上下两个上部和下部 保护环可旋转地联接，用于分离晶片，固定元件（42,44），用于一体地固定上，下保护环，固定用于使上下保护环反转的旋转轴（52,54），同时通过 固定元件的外表面，形成有用于插入各个固定元件的端部的插入槽（62）和用于固定和输送晶片的输送元件的固定卡盘（60），而不会损坏晶片的两侧。

公开(公告)号：KR1019990010763A

公开(公告)日：1999-02-18

申请号：KR1019970033638

申请日：1997-07-18

Applicant: 삼성전자주식회사

Inventor： 전석배 ,  김정한

IPC: G11C5/14

Abstract: 반도체 메모리장치의 내부 전원전압 발생기가 개시된다. 상기 내부 전원전압 발생기는, 전원전압으로 외부 전원전압이 사용되고 기준전압을 입력으로 하여 내부 전원전압을 발생하는 내부 전원전압 발생부와, 상기 내부 전원전압 발생부의 전원 공급능력을 가변하는 전원 제어부를 구비하는 것을 특징으로 한다. 따라서 상기 내부 전원전압 발생기는, 내부 전원전압 발생부의 전원 공급능력을 가변하는 전원 제어부를 구비함으로써, 전류소모가 크게 증가하지 않으면서 IVCC 딥을 방지할 수 있는 장점이 있다.

公开(公告)号：KR1020020006363A

公开(公告)日：2002-01-19

申请号：KR1020000039990

申请日：2000-07-12

Applicant: 삼성전자주식회사

Inventor： 이형용 ,  전석배 ,  박충선 ,  소병환

IPC: G11C29/00

Abstract: PURPOSE: A data input/output circuit of a high speed semiconductor memory device having an output pipeline structure for a burn-in test is provided, which can apply continuous burn-in stress by one column signal by connecting each output pipeline selectively during a burn-in test. CONSTITUTION: The first output pipeline(RP0) comprises the first latch part(LAT0) and transmission gates(TG30,TG30N), and the first latch part comprises eight latches(L0-L7). Also, the second output pipeline(RP1) comprises the second latch part(LAT1) and transmission gates(TG31,TG31N). A transmission gate(TG30) inputs a test mode signal(PCON) and an inverted test mode signal(/PCON) as a transmission control signal and is turned on during a test mode. That is, the transmission gate receives an output of a latch(L7) as an input and transfers inputted data to an input(IN1) of the second latch part in response to the test mode signal and the inverted test mode signal. A transmission gate(TG30N) is turned on when the test mode signal is not enabled and transfers the output of the latch(L7) of the first latch part to a DQ terminal.

Abstract translation: 目的：提供具有用于老化测试的输出管线结构的高速半导体存储器件的数据输入/输出电路，其可以通过在烧录期间选择性地连接每个输出管线而通过一列信号施加连续老化应力 在测试 构成：第一输出管道（RP0）包括第一锁存部分（LAT0）和传输门（TG30，TG30N），第一锁存部分包括八个锁存器（L0-L7）。 此外，第二输出流水线（RP1）包括第二锁存部分（LAT1）和传输门（TG31，TG31N）。 传输门（TG30）输入测试模式信号（PCON）和反相测试模式信号（/ PCON）作为传输控制信号，并在测试模式下导通。 也就是说，传输门接收锁存器（L7）的输出作为输入，并且响应于测试模式信号和反相测试模式信号将输入的数据传送到第二锁存器部分的输入端（IN1）。 当测试模式信号未使能时，传输门（TG30N）导通，并将第一锁存器部分的锁存器（L7）的输出传送到DQ端子。

公开(公告)号：KR1020010035839A

公开(公告)日：2001-05-07

申请号：KR1019990042600

申请日：1999-10-04

Applicant: 삼성전자주식회사

Inventor： 이형용 ,  김상철 ,  전석배

IPC: G11C11/407

CPC classification number: G11C7/222 ,  G11C11/4076 ,  G11C29/48 ,  H03L7/08

Abstract: PURPOSE: A semiconductor memory device having a delay locked loop is provided which is capable of testing the entire part of the semiconductor memory device even in a test mode using a low-frequency test equipment. CONSTITUTION: A semiconductor memory device using an inner clock synchronized with an external clock includes a delay locked loop(12) for generating the inner clock that is phase-synchronized with a reference clock, a frequency multiplier(14) for M-multiplying the frequency of the external clock to generate a multiplied clock, and a selector(16) for selecting one of the external clock and the multiplied clock in response to a predetermined control signal to provide the reference clock. The control signal that is a signal generated inside the semiconductor memory device is enabled when the semiconductor memory device is introduced into a low-speed mode. The low-speed ode corresponds to a burn-in test mode.

Abstract translation: 目的：提供一种具有延迟锁定环路的半导体存储器件，其即使在使用低频测试设备的测试模式下也能测试半导体存储器件的整个部分。 构成：使用与外部时钟同步的内部时钟的半导体存储器件包括用于产生与参考时钟相位同步的内部时钟的延迟锁定环（12），用于将频率M乘以的倍频器（14） 的外部时钟以产生相乘的时钟;以及选择器（16），用于响应于预定的控制信号选择外部时钟和相乘的时钟之一以提供参考时钟。 当半导体存储器件被引入低速模式时，作为半导体存储器件内部产生的信号的控制信号被使能。 低速ode对应于老化测试模式。

公开(公告)号：KR100343143B1

公开(公告)日：2002-07-05

申请号：KR1020000044578

申请日：2000-08-01

Applicant: 삼성전자주식회사

Inventor： 이형용 ,  전석배 ,  박충선

IPC: G11C29/00

Abstract: 비트 라인 불량 검출을 위한 센스 앰프 제어 회로를 구비하는 반도체 메모리 장치 및 그의 제어 방법이 개시된다. 본 발명에 따른 반도체 메모리 장치는, 다수의 워드 라인들과, 다수의 비트 라인들에 연결된 메모리 셀들을 구비하는 반도체 메모리 장치에 있어서, 로우 어드레스 스트로브 신호 지연부, 센스 앰프 제어 신호 발생부, 다수의 제1센스 앰프들 및 다수의 제2센스 앰프들을 구비한다. 로우 어드레스 스트로브 신호 지연부는, 로우 어드레스 스트로브 신호를 소정 시간 지연시키고, 지연된 신호를 출력한다. 센스 앰프 제어 신호 발생부는, 지연된 로우 어드레스 스트로브 신호와 소정의 테스트 모드 제어 신호에 응답하여 생성되고, 반도체 메모리 장치의 동작 모드에 따라서 서로 같은 시점 또는 다른 시점에 인에이블되는 제1 및 제2센스 앰프 제어 신호를 생성한다. 제1센스 앰프들은 제1센스 앰프 제어 신호에 응답하여 비트 라인들 중 2N-1(여기에서, N은 1 이상의 자연수)번째 비트라인 쌍들의 전위를 감지 증폭한다. 제2센스 앰프들은 제2센스 앰프 제어 신호에 응답하여 비트 라인들 중 2N번째 비트 라인 쌍들의 전위를 감지 증폭한다.
본 발명에 따르면, 비트 라인과 인접한 비트 라인 간의 센싱 시점을 서로 다르게 함으로써, 비트 라인 브리지 불량을 보다 정확하게 검출할 수 있을 뿐만 아니라 불량 검출 확률을 높일 수 있다.

公开(公告)号：KR1020020038863A

公开(公告)日：2002-05-24

申请号：KR1020000068730

申请日：2000-11-18

Applicant: 삼성전자주식회사

Inventor： 이형용 ,  전석배

IPC: G11C29/00

Abstract: PURPOSE: A test data generation circuit and a method for generating test data for testing a semiconductor memory device are provided, which generates various test data formats, without increasing the number of data input/output pads used in a write operation of test data. CONSTITUTION: The test data generation circuit comprises a data input pipe line(200) and at least one data phase inverter parts(210,211). The data input pipe line includes the first and the second data input pad(DQA,DQB), a plurality of first latches(L0,L2,L4,L6) connected to the first data input pad and a plurality of the second latches(L1,L3,L5,L7) connected to the second data input pad. The data phase inverter parts are connected between the first data input pad and the plurality of the first latches or between the second data input pad and the plurality of the second latches, and invert a phase of write data inputted through the first or the second data input pad. Data bus lines(W ,W ,W ,W ) connected to the first data input pad are connected to the first latches of the data input pipe line, and data bus lines(W ,W ,W ,W ) connected to the second data input pad are connected to the second latches of the data input pipe line.

Abstract translation: 目的：提供测试数据生成电路和用于产生用于测试半导体存储器件的测试数据的方法，其生成各种测试数据格式，而不增加在测试数据的写入操作中使用的数据输入/输出焊盘的数量。 构成：测试数据生成电路包括数据输入管线（200）和至少一个数据相位逆变器部件（210,211）。 数据输入管线包括第一和第二数据输入焊盘（DQA，DQB），连接到第一数据输入焊盘的多个第一锁存器（L0，L2，L4，L6）和多个第二锁存器（L1 ，L3，L5，L7）连接到第二数据输入板。 数据相位逆变器部分连接在第一数据输入焊盘和多个第一锁存器之间或第二数据输入焊盘与多个第二锁存器之间，并且反转通过第一或第二数据输入的写数据的相位 输入板 连接到第一数据输入焊盘的数据总线（W 0，W 2，W 4，W 6）连接到数据输入管线的第一个锁存器，数据总线（W 连接到第二数据输入板的<1>，W 3，W 5，W 7）连接到数据输入管线的第二锁存器。

公开(公告)号：KR1020020025385A

公开(公告)日：2002-04-04

申请号：KR1020000057121

申请日：2000-09-28

Applicant: 삼성전자주식회사

Inventor： 이형용 ,  전석배 ,  구광모

IPC: G11C11/409

CPC classification number: G11C7/1078 ,  G11C5/147

Abstract: PURPOSE: An input receiver circuit is provided to enable a reference voltage to shift in an input margin improved direction based on a voltage level of input data. CONSTITUTION: An input receiver(200) comprises a voltage pull-up part(210) which increases a voltage level of a reference voltage(VREF) in response to a predetermined voltage level of input data(DIN). A differential amplifier(250) compares the input data with the reference voltage, and amplifies the voltage level of the input data according to a comparison result. The voltage pull-up part(210) includes a PMOS transistor(220) and a load(230).

Abstract translation: 目的：提供一种输入接收器电路，使得参考电压可以根据输入数据的电压电平在输入边缘改进方向上移位。 构成：输入接收器（200）包括电压上拉部分（210），其响应于输入数据（DIN）的预定电压电平而增加参考电压（VREF）的电压电平。 差分放大器（250）将输入数据与参考电压进行比较，并根据比较结果放大输入数据的电压电平。 电压上拉部分（210）包括PMOS晶体管（220）和负载（230）。