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公开(公告)号：KR101580897B1
公开(公告)日：2015-12-30
申请号：KR1020080097941
申请日：2008-10-07
Applicant: 삼성전자주식회사
CPC classification number: G09G3/3648 , G09G3/3688 , G09G2300/0426 , G09G2310/08 , G09G2330/021 , G09G2330/06 , G09G2370/08 , G09G2370/14
Abstract: 타이밍컨트롤러및 디스플레이드라이버간의신호전송방법과이를이용한드라이버모듈및 디스플레이장치가개시된다. 본발명의실시예에따른타이밍컨트롤러와디스플레이드라이버간의신호전송인터페이스는, 디스플레이드라이버내부에위상동기루프(PLL) 또는지연동기루프(DLL)를내장하고저속도의클록을모든디스플레이드라이버각각이공유할수 있도록멀티드롭방식으로제공한다. 따라서, 클록라인수를최소로하여 PCB 레이어수를줄이고전자파장해를감소시킴으로써전력소모및 소자면적을최소로할 수있다.
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公开(公告)号：KR1020100038825A
公开(公告)日：2010-04-15
申请号：KR1020080097941
申请日：2008-10-07
Applicant: 삼성전자주식회사
CPC classification number: G09G3/3648 , G09G3/3688 , G09G2300/0426 , G09G2310/08 , G09G2330/021 , G09G2330/06 , G09G2370/08 , G09G2370/14
Abstract: PURPOSE: A timing controller, a display driver and a driver module and a display device having the same, and a method for transferring a signal are provided to improve EMI by reducing the number of PCB layer. CONSTITUTION: A timing controller comprises a clock generator(21) and a data processing unit(22). The clock generator receives a first clock. The clock generator generates a second clock. The clock generator transmits the second clock to a plurality of display drivers. The data processing unit changes data. The data processing unit distributes transformed data into a plurality of display drivers.
Abstract translation: 目的：提供定时控制器，显示驱动器和驱动器模块以及具有该控制器的显示装置和用于传送信号的方法，以通过减少PCB层的数量来改善EMI。 构成：定时控制器包括时钟发生器（21）和数据处理单元（22）。 时钟发生器接收第一个时钟。 时钟发生器产生第二个时钟。 时钟发生器将第二时钟发送到多个显示驱动器。 数据处理单元更改数据。 数据处理单元将变换后的数据分配给多个显示驱动器。
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公开(公告)号：KR1020090075044A
公开(公告)日：2009-07-08
申请号：KR1020080000803
申请日：2008-01-03
Applicant: 삼성전자주식회사
Abstract: A display driver integrated circuit is provided to reduce data transmission speed between a timing controller and a display circuit by reducing a lock time of a delay locked loop. Source drivers(210, 220, 230) operate a panel by using a data signal and a clock signal from a timing controller. Clock signal generators(211, 221, 231) generate an arranged clock signal to drive the operation panel, and a coast signal generator(240) generates a coast signal having more than one active section by corresponding to the operation of a source driver, and controls the arrangement of clock signal generator in the active section disable.
Abstract translation: 提供了一种显示驱动器集成电路，通过减少延迟锁定环的锁定时间来减少时序控制器和显示电路之间的数据传输速度。 源驱动器（210,220,230）通过使用来自定时控制器的数据信号和时钟信号来操作面板。 时钟信号发生器（211,221,231）生成布置的时钟信号以驱动操作面板，并且滑行信号发生器（240）通过对应于源驱动器的操作产生具有多于一个有效部分的滑行信号，以及 控制主动部分中时钟信号发生器的布置禁用。
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