Abstract:
핸들러(handler)에 대한 제반 설정 사항을 네트워킹을 통해 원격 제어하여 반도체 소자의 검사효율을 높일 수 있는 핸들러 원격 제어가 가능한 반도체 소자의 검사 시스템 및 그 작동방법에 관해 개시한다. 이를 위해 본 발명은 테스터와 핸들러를 연결하는 GPIB(General Purpose Instruction Bus) 통신케이블을 통해 반도체 소자의 전기적 검사를 위한 기본 통신 데이터와, 핸들러 원격제어를 위한 통신 데이터와, 핸들러 상태 점검을 위한 통신 데이터를 서로 송수신한다. 전기적 검사, GPIB 통신 케이블, 핸들러 원격제어.
Abstract:
A data processing method of a semiconductor test facility is provided to preferentially process data of semiconductor elements, which are inspected in a specific station, when the specific station finishes a test process and then transmits a data processing signal. A data processing method of a semiconductor test facility for testing semiconductor elements in plural stations includes steps of: receiving a signal from the stations(S110); judging whether the signal is a test requiring signal or a data processing signal(S120); executing a test process if for the test requiring signal and stopping the test process of the other station if for the data processing signal(S130,S140,S170); processing and storing data of the semiconductor elements, which are completely inspected in the specific station(S150); executing the test process of the other station again(S160); and performing the test process of the specific station again.
Abstract:
DUT 보드에 탑재된 소켓(socket)의 이상 유무를 실시간으로 점검할 수 있는 반도체 소자의 전기적 검사방법에 관해 개시한다. 이를 위해 본 발명은 테스터(tester)에서 전기적 검사를 수행한 후, 소켓의 이상 유무를 판단할 수 있는 전기적 검사 결과를 누적시키고, 이를 소켓의 이상 유무를 판단할 수 있는 기준값과 비교하여 DUT 보드에 장착된 복수개의 소켓에 대한 사용 가능 여부를 판단하여, 판단결과를 핸들러에 송신함으로써 DUT(Device Under Test) 보드에서 결함이 있는 소켓의 사용을 중지시킨다.
Abstract:
A method for continuous electrical testing throughout an identification of a lot and a test tray is provided to enhance the uptime of a tester and to reduce the number of testers. A plurality of lots are continuously loaded on a handler(H100). Semiconductor devices of the lots are transferred from a customer tray to a test tray by using a loader of the handler. The identification information on each semiconductor device of the test tray is stored in the handler and transmitted to a server connected with a tester(H110). An electrical test is started on the semiconductor device in the handler and tester by using the identification information(T110).
Abstract:
PURPOSE: A method for inspecting a scrap of a semiconductor device is provided to enhance the inspection efficiency by inspecting simultaneously 64 semiconductor devices or 128 semiconductor devices. CONSTITUTION: A customer tray including plural semiconductor devices is loaded(50). The semiconductor devices are loaded on a buffer tray of a loader part(52). The semiconductor devices are transferred to a test tray(54). The test tray including the semiconductor devices is transferred to a test site(56). The semiconductor devices are inspected(58). The semiconductor devices are transferred to a customer tray of an unloader part(60). A customer tray of the loader part is checked(62). The number of semiconductor devices loaded on the last buffer tray of the loader part is counted(64). The number of semiconductor devices are compared with a scrap reference value(66). The semiconductor devices are transferred to the test array if the number of semiconductor devices is larger than the scrap reference value(68). The semiconductor devices are inspected and classified(70). A retest mode is operated(72). A retest process is performed(74-78).
Abstract:
PURPOSE: An electrical test method of a semiconductor device for performing a real-time decision process for an abnormal state of a socket is provided to mend or exchange efficiently the socket by checking correctly a state of the socket. CONSTITUTION: A tester and a handler load a DUT(Device Under Test) into a test site of the handler connected to a DUT board(S100). An electrical test for the DUT is performed by operating the tester(S110). The tester collects test results of each socket of the DUT board(S120). The test results of each socket of the DUT board are stored into a storage unit of the tester(S130). The test results of each socket are partially transmitted to the handler and the handler processes the DUT according to the received test results(S140). The test results are compared with the reference value(S150). Each state of the sockets of the DUT board is decided by the compared result(S160). The decided result is transmitted to the handler and the handler interrupts operations of bad sockets(S170).
Abstract:
본 발명은 반도체 소자의 검사 방법을 제공한다. 본 발명은 로더부의 커스터머 트레이가 비어 있지 않으면 상기 피검사 반도체 소자의 검사 과정을 진행하고, 비어 있으면 로더측 버퍼부의 버퍼 트레이에 탑재된 피검사 반도체 소자의 수를 카운트한다. 상기 로더측 버퍼부의 버퍼 트레이에 탑재된 피검사 반도체 소자의 수와 테스터부에 미리 입력된 자투리 기준값과 비교판단한다. 상기 피검사 반도체 소자의 수가 자투리 기준값보다 크면 상기 버퍼 트레이에 탑재된 피검사 반도체 소자의 검사를 진행하고 그렇지 않으면 중지한다. 상기 검사가 중지된 상기 테스터는 재검사 모드를 시작한다. 상기 불량으로 판정된 반도체 소자를 자투리 피검사 반도체 소자가 남아있는 버퍼 트레이에 탑재하여 재검사한다.
Abstract:
A system and method automatically analyzes and manages loss factor data of test processes in which a great number of IC devices are tested as a lot with a number of testers. The lot contains a predetermined number of identical IC devices, and the lot test process is performed sequentially according to a predetermined number of test cycles. The system include a means for verifying test results for each of the test cycles and for determining whether or not a re-test is to be performed and an IC device loading/unloading means for loading IC devices to be tested and contained in the lot to a test head and for unloading the tested IC devices from the test head by sorting the tested IC devices according to the test results. The system also includes raw data generating means for generating raw data on the basis of time data occurring when the test process is performed; data calculating means for calculating testing time data, index time data based on the raw data, and loss time data; data storage means for storing the raw data and the calculated data; and data analyzing and outputting means for analyzing the raw data and the calculated data according to the lots, the plurality of testers and the IC device loading/unloading means and for outputting the analyzed output through an user interface. The test system includes testers, a server system and terminal computer, and the server system is provided with data storage means for integrally manipulating time data generated by the testers according to lots and test cycles and for storing manipulated time data.
Abstract:
PURPOSE: A test method for improving an operation ratio of test equipment is provided to enhance the operation ratio of the test equipment by reducing a test idling period of time including a retest time, a loading time, and an unloading time. CONSTITUTION: The first lot is loaded by using a test handler(202). The first cycle test and the main item test are performed(204,206). In the main item test, two or more other lots are loaded. The other lots are merged with the first lot by inputting numbers and quantities of the other lots(208). The main item test for the first lot and the other lots is performed(210). A retest process for bad semiconductor devices is performed(212). The last cycle test is performed(214). The retest process is finished(216).
Abstract:
PURPOSE: A test apparatus provided with at least two set test boards in one handler and a method for testing the same are provided to reduce the size thereof since the semiconductor devices loaded on the test board are tested by providing with at least two test boards. CONSTITUTION: A test apparatus provided with at least two set test boards in one handler includes a handler(200) provided with a test head(210) and a head board. The test head(210) counts the test cycles supplied from the tester and divides the counted cycles into an odd number signal and an even number signal. The plurality of semiconductor devices is loaded on the first site(222) and the second site(224), separately. And, the head board is selectively tested in response to the odd number signal and the even number signal.