公开(公告)号：KR1020080098238A

公开(公告)日：2008-11-07

申请号：KR1020070043665

申请日：2007-05-04

Applicant: 삼성전자주식회사

Inventor： 정양호 ,  강훈 ,  김재성 ,  이희국

IPC: G02F1/136

CPC classification number: G02F1/1362 ,  G02F1/134309 ,  G02F2201/123 ,  H01L27/124 ,  H01L29/785

Abstract: A method for manufacturing a display device is provided to improve the productivity manufacture efficiency. An insulating layer pattern including the negative photoresist is formed on the base substrate where the pixel region is defined. A first light is irradiated to the insulating layer pattern. A shape of the insulating layer pattern is controlled by generating the reflow heat-treating according to the energy of the first light. A pixel electrode is formed on the insulating layer corresponds to each pixel region. The insulating layer pattern is the organic insulating layer.

Abstract translation: 提供一种用于制造显示装置的方法以提高生产率制造效率。 在限定像素区域的基底基板上形成包括负性光致抗蚀剂的绝缘层图案。 第一光照射到绝缘层图案。 通过根据第一光的能量产生回流热处理来控制绝缘层图案的形状。 在绝缘层上形成像素电极对应于每个像素区域。 绝缘层图案是有机绝缘层。

公开(公告)号：KR1020080000794A

公开(公告)日：2008-01-03

申请号：KR1020060058589

申请日：2006-06-28

Applicant: 삼성전자주식회사

Inventor： 강훈 ,  김재성 ,  정양호 ,  이희국

IPC: H01L21/324 ,  H01L21/477

CPC classification number: H01L21/324 ,  H01L21/67098 ,  H01L21/687

Abstract: A baking device and a substrate baking method are provided to decrease a temperature variation between a pin contact region and the rest region by changing a contact position between a support pin and a plate. A baking device includes a plate(11) and a support pin(12). At least one pin hole is formed on the plate, which receives power and supplies heat to a substrate(20). A photoresist film is coated on the substrate. The support pin is inserted into the pin hole, and arranges the substrate to be apart from the plate by a predetermined distance. The support pin includes a body portion(13) and a ball bearing(14). The body portion is coupled with the plate through the pin hole. A hemispherical groove is formed on an end portion of the main body, which is adjacent to the substrate. The ball bearing is arranged in the hemispherical groove.

Abstract translation: 提供一种烘烤装置和基板烘烤方法，通过改变支撑销和板之间的接触位置来减小针接触区域与其余区域之间的温度变化。 烘烤装置包括板（11）和支撑销（12）。 在板上形成至少一个销孔，其接收动力并将热量供给到基板（20）。 光刻胶膜涂在基片上。 支撑销插入销孔，并将基板与板隔开预定距离。 支撑销包括主体部分（13）和滚珠轴承（14）。 主体部分通过销孔与板连接。 半导体槽形成在与基板相邻的主体的端部上。 球轴承布置在半球形凹槽中。

公开(公告)号：KR1020080053551A

公开(公告)日：2008-06-16

申请号：KR1020060125251

申请日：2006-12-11

Applicant: 삼성전자주식회사

Inventor： 강훈 ,  김재성 ,  정양호

IPC: H01L21/027 ,  H01L21/66

CPC classification number: G03F7/70633 ,  G03F9/7073 ,  G03F9/7088 ,  H01L23/544 ,  H01L2223/54426

Abstract: A method for manufacturing an array substrate and a method for testing the same are provided to quantitatively detect misalignment of second and third pattern layers by comparing designed value with actually measured resistance, thereby achieving reduction in test time while easily measuring the misalignment. A method for manufacturing an array substrate comprises the steps of: forming a first pattern layer including a plurality of gate lines corresponding to a plurality of array substrate regions that are defined within a mother substrate; forming a plurality of data lines defining unit pixels within the array substrate region by crossing the gate lines on the mother substrate on which the first pattern layer is formed, and a second pattern layer including a data align key(143) on a partial region of the mother substrate, which comprises a first vernier(146) and a first contact terminal(147) connected to the first vernier; forming a pixel electrode(161) corresponding to the unit pixel on the mother substrate on which the second pattern layer is formed, and a third pattern layer including an electrode align key(163) partially superposed with the data align key, and comprising a second vernier(166) and a second contact terminal(167) connected to the second vernier.

Abstract translation: 提供一种阵列基板的制造方法及其测试方法，通过将设计值与实际测量的电阻进行比较来定量检测第二和第三图案层的未对准，从而实现测试时间的缩短，同时容易地测量不对准。 一种阵列基板的制造方法，其特征在于，包括：形成第一图案层，所述第一图案层包括对应于在母基板内限定的多个阵列基板区域的多条栅极线; 通过使形成有第一图案层的母基板上的栅极线交叉而形成在阵列基板区域内定义单位像素的多个数据线，以及包括数据对准键（143）的第二图案层 母基板，其包括连接到第一游标器的第一游标器（146）和第一接触端子（147）; 形成与形成有第二图案层的母基板上的单位像素对应的像素电极（161），以及包括与数据对准键部分重叠的电极对准键（163）的第三图案层，并且包括第二 游标（166）和连接到第二游标的第二接触端子（167）。

公开(公告)号：KR1020080043092A

公开(公告)日：2008-05-16

申请号：KR1020060111688

申请日：2006-11-13

Applicant: 삼성전자주식회사

Inventor： 김도현 ,  이은국 ,  임순권 ,  정창오 ,  이제훈 ,  정양호

IPC: G02F1/136

CPC classification number: G02F1/136 ,  G02F1/13458 ,  G02F2201/123 ,  H01L29/786

Abstract: A thin film transistor substrate and a method for manufacturing the thin film transistor substrate are provided to form a passivation layer on a thin film transistor using organic material to prevent reduction of zinc oxide, maintain current and voltage characteristics of a zinc oxide semiconductor and insulate the thin film transistor from a pixel electrode. A thin film transistor substrate includes a gate line(14), a data line(24), a thin film transistor, a pixel electrode(42), and an organic passivation layer. The gate line and the data line formed on a substrate crossing each other to define a pixel region. The thin film transistor is connected to the gate line and the data line and includes a zinc oxide semiconductor. The pixel electrode is connected to the thin film transistor. The organic passivation layer is formed between the thin film transistor and the pixel electrode and made of siloxane or BCB(Benzocyclobutene).

Abstract translation: 提供薄膜晶体管基板和制造薄膜晶体管基板的方法，以在有机材料的薄膜晶体管上形成钝化层，以防止氧化锌的还原，保持氧化锌半导体的电流和电压特性并使 薄膜晶体管从像素电极。 薄膜晶体管基板包括栅极线（14），数据线（24），薄膜晶体管，像素电极（42）和有机钝化层。 形成在衬底上的栅极线和数据线彼此交叉以限定像素区域。 薄膜晶体管连接到栅极线和数据线，并且包括氧化锌半导体。 像素电极连接到薄膜晶体管。 有机钝化层形成在薄膜晶体管和像素电极之间，由硅氧烷或BCB（苯并环丁烯）制成。

公开(公告)号：KR1020080015619A

公开(公告)日：2008-02-20

申请号：KR1020060077198

申请日：2006-08-16

Applicant: 삼성전자주식회사

Inventor： 박정인 ,  박정민 ,  전우석 ,  정양호

IPC: H01L21/027 ,  H01L29/786

CPC classification number: G03F1/54 ,  G03F7/70433 ,  H01L21/0337 ,  H01L29/78618

Abstract: A mask and a method for manufacturing a thin film transistor display panel using the mask are provided to form a photoresist pattern with an intermediate thickness by using a mask including a shielding layer on a partial region in a semi-transmitting section. Gate lines(121,129) including a gate electrode(124) are formed on a dielectric substrate. A gate dielectric covering the gate lines is formed. A semiconductor(154) is formed on an upper portion of the gate dielectric. A data line(171) having a source electrode and a drain electrode(175) are formed on an upper portion of the semiconductor. A protective layer having contact holes(181,182,185) is formed. The contact holes cover the data line and expose the drain electrode. A pixel electrode is formed to be connected to the drain electrode through the contact holes. A photolithography process is performed by using a mask to form the semiconductor, the data line, and the drain electrode. The mask includes a transmitting section, a semi-transmitting section, and a shielding section. The semi-transmitting section includes a semi-transmitting layer. A shielding layer is formed on a partial region in the semi-transmitting section.

Abstract translation: 提供了一种使用掩模制造薄膜晶体管显示面板的掩模和方法，以通过在半透射部分中的部分区域上使用包括屏蔽层的掩模来形成具有中间厚度的光致抗蚀剂图案。 包括栅极（124）的栅线（121,129）形成在电介质基板上。 形成覆盖栅极线的栅极电介质。 半导体（154）形成在栅极电介质的上部。 在半导体的上部形成具有源电极和漏电极（175）的数据线（171）。 形成具有接触孔（181,182,185）的保护层。 接触孔覆盖数据线并露出漏电极。 像素电极形成为通过接触孔与漏电极连接。 通过使用掩模来形成光刻工艺以形成半导体，数据线和漏电极。 掩模包括发射部分，半透射部分和屏蔽部分。 半透射部分包括半透射层。 在半透射部分的部分区域上形成屏蔽层。

公开(公告)号：KR1020090095988A

公开(公告)日：2009-09-10

申请号：KR1020080021286

申请日：2008-03-07

Applicant: 삼성전자주식회사

Inventor： 정양호 ,  강훈 ,  김재성 ,  이희국

IPC: G02F1/136 ,  H01L29/786

CPC classification number: H01L27/1248 ,  H01L27/1288 ,  G02F1/136227 ,  H01L27/1214

Abstract: A display substrate reducing manufacturing cost and a manufacturing method thereof are provided to simplify a manufacturing process by removing the manufacturing process patterning pixel electrode. A first transparent conductive layer(183) is directly contacted on an upper part of a gate line(111). A second transparent conductive layer(185) is directly contacted on the top of the data line. A switching device is connected to the gate wiring and data line. An organic film is formed on the base substrate. A first trench corresponding to the first transparent conductive layer and the second trench corresponding to the second transparent conductive layer are formed. A pixel electrode is formed in the pixel region above the organic film.

Abstract translation: 提供了降低制造成本的显示基板及其制造方法，以通过去除制造工艺图案化像素电极来简化制造工艺。 第一透明导电层（183）在栅极线（111）的上部直接接触。 第二透明导电层（185）在数据线的顶部直接接触。 开关器件连接到栅极布线和数据线。 在基底基板上形成有机膜。 形成对应于第一透明导电层和对应于第二透明导电层的第二沟槽的第一沟槽。 像素电极形成在有机膜上方的像素区域中。

公开(公告)号：KR1020080056861A

公开(公告)日：2008-06-24

申请号：KR1020060129933

申请日：2006-12-19

Applicant: 삼성전자주식회사

Inventor： 강훈 ,  김재성 ,  정양호 ,  이희국

IPC: G03F7/028 ,  G03F7/027 ,  G03F7/004

CPC classification number: G03F7/0757 ,  G03F7/0045 ,  G03F7/027 ,  G03F7/028 ,  G03F7/0382

Abstract: A negative photoresist composition is provided to form an organic insulation layer having a high transmissivity and to reduce the residue of an organic insulation layer, thereby improving the quality of a display device. A negative photoresist composition comprises an acrylic copolymer obtained by reacting a monomer comprising an unsaturated carboxylic acid and an unsaturated compound containing an epoxy group; a photoinitiator; a crosslinking agent; a silicone-based surfactant; and a solvent, wherein the content of solid part is 10-40 wt%, the content of the acrylic copolymer, the photoinitiator and the crosslinking agent is 25-70 wt%, 5-25 wt% and 10-50 wt% based on the weight of the total solid part, and the content of the silicone-based surfactant is 0.02-3 wt% based on the total weight.

Abstract translation: 提供负性光致抗蚀剂组合物以形成具有高透射率的有机绝缘层并减少有机绝缘层的残余物，从而提高显示装置的质量。 负性光致抗蚀剂组合物包含通过使包含不饱和羧酸的单体和含有环氧基的不饱和化合物反应而获得的丙烯酸共聚物; 光引发剂; 交联剂; 硅氧烷基表面活性剂; 和溶剂，其中固体部分的含量为10-40重量％，丙烯酸共聚物，光引发剂和交联剂的含量为25-70重量％，5-25重量％和10-50重量％，基于 总固体重量，硅氧烷系表面活性剂的含量占总重量的0.02-3重量％。

公开(公告)号：KR1020080049951A

公开(公告)日：2008-06-05

申请号：KR1020060120571

申请日：2006-12-01

Applicant: 삼성전자주식회사

Inventor： 강훈 ,  김재성 ,  정양호 ,  이희국 ,  채종철

IPC: H01L21/027

CPC classification number: G03F1/72 ,  G03F1/32

Abstract: A method for repairing a half-tone mask and a method for manufacturing a thin film transistor device thereby are provided to uniformly form light transmittance by forming a repair part with a lattice pattern. A gate pattern including a gate line and a gate electrode(20) are formed on a transparent substrate(10). A gate insulating layer(30) is formed on the substrate having the gate pattern. An active layer(40), a source electrode(60), and a drain electrode(70) are formed on the gate insulating layer. A data line(50) is connected to the source electrode. An ohmic contact layer is formed between the active layer, the source electrode, and the drain electrode. A data pattern is formed by performing a mask process using a single slit mask. A protective layer(80) having a contact hole(90) is formed by performing a mask process. A pixel electrode(135) is formed by performing a mask process.

Abstract translation: 提供了修补半色调掩模的方法和由此制造薄膜晶体管器件的方法，以通过形成具有格子图案的修复部分来均匀地形成透光率。 在透明基板（10）上形成包括栅极线和栅电极（20）的栅极图案。 在具有栅极图案的基板上形成栅极绝缘层（30）。 在栅极绝缘层上形成有源层（40），源电极（60）和漏电极（70）。 数据线（50）连接到源电极。 在有源层，源电极和漏电极之间形成欧姆接触层。 通过使用单个狭缝掩模执行掩模处理来形成数据图案。 通过进行掩模处理形成具有接触孔（90）的保护层（80）。 通过进行掩模处理形成像素电极（135）。

公开(公告)号：KR1020080043566A

公开(公告)日：2008-05-19

申请号：KR1020060112277

申请日：2006-11-14

Applicant: 삼성전자주식회사

Inventor： 김재성 ,  강훈 ,  정양호 ,  이희국

IPC: G02F1/136

CPC classification number: G02F1/136227 ,  G02B1/14 ,  G02F1/136286 ,  G02F2201/123 ,  H01L29/786

Abstract: A TFT(Thin Film Transistor) substrate and a method for manufacturing the same are provided to simplify a manufacturing process by omitting an inorganic insulation layer process. A method for manufacturing a thin film transistor substrate includes steps of: forming a thin film transistor(TFT) on a substrate(10); heating the siloxane based inorganic passivation layer; forming a contact hole piercing the siloxane based inorganic passivation layer; and forming a pixel electrode(42) on the siloxane based inorganic passivation layer to be coupled with a drain electrode(28) of the thin film transistor. A heat treatment for the siloxane based inorganic passivation layer is performed at a high temperature after a formation of the contact hole.

Abstract translation: 提供TFT（薄膜晶体管）基板及其制造方法，以通过省略无机绝缘层工艺来简化制造工艺。 制造薄膜晶体管基板的方法包括以下步骤：在基板（10）上形成薄膜晶体管（TFT）; 加热硅氧烷基无机钝化层; 形成穿透硅氧烷基无机钝化层的接触孔; 以及在所述硅氧烷基无机钝化层上形成与所述薄膜晶体管的漏电极（28）耦合的像素电极（42）。 在形成接触孔之后，在高温下进行基于硅氧烷的无机钝化层的热处理。