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公开(公告)号：KR100926566B1
公开(公告)日：2009-11-12
申请号：KR1020070126234
申请日：2007-12-06
CPC classification number: H04L25/067 , H04L25/03006 , H04L2025/03426
Abstract: 본 발명은 연판정값 산출 방법 및 송신 신호 검출 방법에 관한 것이다.
본 발명은 수신된 신호에 기초해 채널을 추정하고, 복수의 데이터 스트림을 재정렬한다. 그리고, 재정렬된 데이터 스트림을 이용하여 복수의 후보 벡터를 선택하고, 각 후보 벡터에 대응하는 메트릭을 산출한다. 그리고, 각 후보 벡터 별로 산출된 메트릭을 이용하여 임계치를 계산하고, 각 후보 벡터에 대응하는 메트릭 및 임계치를 이용하여 송신 신호의 각 비트에 대한 연판정값을 산출한다.
연판정값, 다중송수신, MIMO, 공간 다중화, 메트릭, 로그우도비-
2.发明公开
公开(公告)号：KR1020090063957A
公开(公告)日：2009-06-18
申请号：KR1020070131497
申请日：2007-12-14
IPC: H04L27/22
CPC classification number: H04L27/22 , H04L27/3863
Abstract: A method and a device for dividing a receiving symbol signal into bit information are provided to perform a bit division process in a two dimensions simply by dividing the PSK(Phase Shift Keying) modulated symbol into the bit information in consideration of BRGC(Bit Reflected Gray Code) characteristic by using a coordinate rotation method. A rotation angle calculator(150) calculates the rotation angle by using each absolute value about I channel and Q channel symbol signals of the receiving signal which is arranged with the interval of the phase angle on a two dimensional concentric circle. A bit information converter(170) extracts the bit information about each of the I channel or Q channel symbol signals which are rotated by using a rotation angle outputted from the rotation angle calculator. An absolute value converter(120) produces each absolute value about the values of the I channel and Q channel symbol signals of the receiving symbol. A phase angle calculator(130) produces a radian phase angle by using each absolute value about the value of I channel and Q channel outputted from the absolute value converter. A symbol arrangement value calculator(140) produces an arrangement value of the symbols comprising the I channel or Q channel symbol signals by using the radian phase angle outputted from the phase angel calculator.
Abstract translation: 提供了一种将接收符号信号分成比特信息的方法和装置，以便通过将PSK（相移键控）调制的符号分解成比特信息来考虑BRGC（比特反射灰色 代码）特性使用坐标旋转法。 旋转角度计算器（150）通过使用在二维同心圆上以相位角间隔排列的接收信号的大约I通道和Q通道符号信号的绝对值来计算旋转角度。 位信息转换器（170）提取关于通过使用从旋转角计算器输出的旋转角旋转的I通道或Q通道符号信号中的每一个的位信息。 绝对值转换器（120）产生关于接收符号的I信道和Q信道符号信号的值的每个绝对值。 相位角计算器（130）通过使用关于从绝对值转换器输出的I通道和Q通道的值的绝对值产生弧度相位角。 符号排列值计算器（140）通过使用从相位角计算器输出的弧度相位角来产生包括I通道或Q通道符号信号的符号的排列值。
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公开(公告)号：KR1020090062715A
公开(公告)日：2009-06-17
申请号：KR1020070130133
申请日：2007-12-13
CPC classification number: G06F11/26
Abstract: A device for testing a modem of a wireless communication system and a method therefor are provided to test the modem which transmits/receives a plurality of signals corresponding to each wireless channel. A signal processing unit(410) controls the power of the first transmission signal. A transmission memory(420) and a reception memory(430) receive and temporarily stores the first transmission signal from the signal processing unit. According to a control signal, a wireless signal processing unit(440) receives or transmits the second received signal. A channel is formed by a plurality of antennas which the mobile station and base station include.
Abstract translation: 提供了用于测试无线通信系统的调制解调器的装置及其方法，用于测试发送/接收与每个无线信道相对应的多个信号的调制解调器。 信号处理单元（410）控制第一发送信号的功率。 发送存储器（420）和接收存储器（430）接收并临时存储来自信号处理单元的第一发送信号。 根据控制信号，无线信号处理单元（440）接收或发送第二接收信号。 信道由移动站和基站所包含的多个天线形成。
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公开(公告)号：KR100874484B1
公开(公告)日：2008-12-18
申请号：KR1020060124509
申请日：2006-12-08
IPC: H03M13/11
Abstract: A quasi-cyclic low density parity check coding method and an apparatus thereof are provided to improve a data processing speed of a high speed by shifting a parity check matrix to a bi-direction. A quasi-cyclic low density parity check coding apparatus includes an input aligning module(210), a parity check matrix input module(220), a row multiplying calculation module(230), a first calculation module(240), a second calculation module(250), and an output aligning module(260). The input aligning module receives and aligns an input bit for a coding. The parity check matrix input module provides a shift index for shifting the aligned input bit. The row multiplying calculation module shifts the input bit to a left or right side based on the shift index, and calculates a first parity part using the shifted input bit. The first calculation module calculates a coding result value for each of components of the input bit using the first parity part. The second calculation module calculates a second parity part from the coding result value calculated by the first parity part and the first calculation module. The output aligning module calculates and outputs the quasi-cyclic low density parity check coding value using the input bit, the first parity part and the second parity part.
Abstract translation: 提供准循环低密度奇偶校验编码方法及其装置，以通过将奇偶校验矩阵移位到双向来提高高速的数据处理速度。 一种准循环低密度奇偶校验编码装置，包括输入对齐模块（210），奇偶校验矩阵输入模块（220），行相乘计算模块（230），第一计算模块（240），第二计算模块 （250）和输出对齐模块（260）。 输入对齐模块接收并对齐编码的输入位。 奇偶校验矩阵输入模块提供用于移位对齐的输入位的移位索引。 行相乘计算模块基于移位索引将输入位移位到左侧或右侧，并且使用移位的输入位来计算第一奇偶校验部分。 第一计算模块使用第一奇偶校验部分计算输入比特的每个分量的编码结果值。 第二计算模块根据由第一奇偶校验部分和第一计算模块计算的编码结果值来计算第二奇偶校验部分。 输出对齐模块使用输入比特，第一奇偶校验部分和第二奇偶校验部分来计算和输出准循环低密度奇偶校验编码值。
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公开(公告)号：KR1020070092559A
公开(公告)日：2007-09-13
申请号：KR1020060022873
申请日：2006-03-10
Applicant: 삼성전자주식회사
Inventor： 최정필
IPC: G06F9/46
CPC classification number: G06F9/45516 , G06F8/52 , G06F9/3009
Abstract: A device and a method for scheduling threads in a virtual machine are provided to prevent deterioration of an interpreter performance without requiring a routine for checking whether each bytecode is scheduled or not, as a time of point in which the threads of the virtual machine is scheduled is based on a counter value of a system clock. A JBT(Java Bytecode Translator) manager(311) converts the bytecode of the virtual machine into a native code and schedules the threads based on the system clock. A database cache(312) stores the converted native code. A B2C cache(313) maps an address of the bytecode to the native code stored in the DB cache. A JBT resister(314) performs communication with a processor and the JBT manager. The JBT manager includes a multiplexer(311a) receiving a counter value of the system clock, and a down-counter(311b) changing the counter value whenever the system clock is received and determining to schedule the thread based on the counter value.
Abstract translation: 提供一种用于在虚拟机中调度线程的设备和方法，以防止解释器性能的恶化，而不需要用于检查每个字节码是否被调度的例程作为虚拟机的线程被调度的时刻 是基于系统时钟的计数器值。 JBT（Java Bytecode Translator）管理器（311）将虚拟机的字节码转换为本地代码，并根据系统时钟调度线程。 数据库高速缓存（312）存储转换的本地代码。 B2C缓存（313）将字节码的地址映射到存储在DB高速缓存中的本机代码。 JBT电阻（314）执行与处理器和JBT管理器的通信。 JBT管理器包括接收系统时钟的计数器值的多路复用器（311a），以及每当收到系统时钟时改变计数器值的递减计数器（311b），并根据该计数器值确定调度线程。
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Patent Agency Ranking
公开(公告)号：KR1020060120312A
公开(公告)日：2006-11-27
申请号：KR1020050042082
申请日：2005-05-19
Applicant: 삼성전자주식회사
IPC: G06F9/00
CPC classification number: G06F9/45516 , G06F9/4484
Abstract: A system and a method for reducing an execution time of a bytecode in a JVM(Java Virtual Machine) are provided to reduce the entire execution time of the bytecode with minimization of access to a stack memory by storing an upper part of the stack memory needed for an operation to a stack register and securing a register area to perform the operation. A database cache(140) stores multiple machine codes converted from the bytecode. A machine code changer(150) changes the machine code into the new machine code by removing a specific instruction from the machine code. A register manager(170) manages a register file(180) which offers stack data needed for the operation of the machine code and the register area for performing the operation. A machine code information storing part(160) stores basic block information for the machine code and spill/fill information for the stack data of the register file. The register manager performs spill for loading the stack data needed for the operation of the machine code to the register file and fill for moving the stack data placed in the register file to secure the register area for performing the operation based on the spill/fill information.
Abstract translation: 提供了用于减少JVM（Java虚拟机）中的字节码执行时间的系统和方法，以通过存储所需的堆栈内存的上部来最小化对堆栈存储器的访问来减少字节码的整个执行时间 用于对堆栈寄存器的操作，并确保寄存器区域执行操作。 数据库缓存（140）存储从字节码转换的多个机器码。 机器代码更换器（150）通过从机器代码中删除特定指令将机器代码更改为新的机器代码。 寄存器管理器（170）管理寄存器文件（180），其提供用于操作机器码所需的堆栈数据和用于执行操作的寄存器区域。 机器代码信息存储部分（160）存储用于机器代码的基本块信息和用于寄存器文件的堆栈数据的溢出/填充信息。 注册管理器执行溢出，将机器代码操作所需的堆栈数据加载到寄存器文件中，并填写移动放置在寄存器文件中的堆栈数据，以确保基于溢出/填充信息执行操作的寄存器区域 。
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公开(公告)号：KR1020010001021A
公开(公告)日：2001-01-05
申请号：KR1019990019981
申请日：1999-06-01
Applicant: 삼성전자주식회사
IPC: B60K28/02
Abstract: PURPOSE: A method for sensing sleepiness by eye-blinking and a method for chasing an eye-area deformed in the process of sleepiness level detection preprocessing are provided to easily detect a sleepiness level under the various circumstances caused by the changes of an original image size and an inclination, and a sudden illumination change, without repeatedly detecting a face area and an eye area for each image. CONSTITUTION: A method for sensing sleepiness by eye-blinking includes the steps of determining an eye position searching area in an input image for detecting eye positions in the eye position searching area by using a template for inspecting characteristics of eyes(310), determining whether the eyes are opened or not by extracting upper and lower border lines of the eyes from the detected eye positions(320), and detecting a sleepiness level indicating a time degree that the eyes are closed by continuously monitoring whether the eyes are opened or not for continuous images(330).
Abstract translation: 目的：提供通过眨眼来感知困倦的方法和用于追踪在睡眠水平检测预处理过程中变形的眼部区域的方法，以容易地检测由原始图像尺寸的变化引起的各种情况下的困倦程度 倾斜和突然的照明变化，而不会重复地检测每个图像的面部区域和眼睛区域。 构成：用于通过眨眼来感测困倦的方法包括以下步骤：通过使用用于检查眼睛特征的模板（310）来确定用于检测眼睛位置搜索区域中的眼睛位置的眼睛位置搜索区域，确定是否 通过从检测到的眼睛位置（320）中提取眼睛的上部和下部边界线来打开或关闭眼睛，并且通过连续监视眼睛是否被打开来检测表示眼睛闭合的时间程度的嗜睡水平 连续图像（330）。
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公开(公告)号：KR101200073B1
公开(公告)日：2012-11-12
申请号：KR1020060124539
申请日：2006-12-08
Applicant: 한국전자통신연구원 , 삼성전자주식회사 , 에스케이브로드밴드주식회사 , 에스케이텔레콤 주식회사 , 주식회사 케이티
Abstract: 본 발명은 와이브로 시스템의 채널 부호기에 관한 것이다.
와이브로 규격에서 채널 부호기는 CRC 부호기, 랜덤화기, CTC 부호기, 인터리버, 심볼선택기 등으로 이루어지고 있다. 본 발명은 각 블록들에 대하여 병렬 데이터 처리를 위한 하드웨어 구조를 제시함으로써, 와이브로 시스템에서 요구하는 고속의 데이터를 효율적으로 처리할 수 있다.
와이브로, CTC, 터보, 부호화, 인터리버-
公开(公告)号：KR1020100065095A
公开(公告)日：2010-06-15
申请号：KR1020090111133
申请日：2009-11-17
IPC: H04B7/04
CPC classification number: H04B1/02 , H04B7/0413 , H04B7/08
Abstract: PURPOSE: A method for detecting signal in MIMO communication system and a device thereof are provided to embody the same performance with method of optimum signal detecting. CONSTITUTION: A detection order determining unit(211) determines symbol location to detect from receiving signals. A symbol candidate selector(212) selects symbol candidate vectors on constellation according to determined symbol location by each level. A symbol detection unit(213) calculates Euclidean distance respectively with the receiving signal about entire constellation symbol candidate vectors combining all optimum number of symbol candidate vectors according to each level.
Abstract translation: 目的：提供一种用于MIMO通信系统中信号检测的方法及其装置，以最佳信号检测方式体现相同的性能。 构成：检测顺序确定单元（211）确定从接收信号检测的符号位置。 符号候选选择器（212）根据每个级别确定的符号位置选择星座上的符号候选向量。 符号检测单元（213）分别根据接收信号，根据每个等级，将组合所有最佳数量的码元候选向量的整个星座符号候选向量计算欧氏距离。
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公开(公告)号：KR1020100064322A
公开(公告)日：2010-06-14
申请号：KR1020090086515
申请日：2009-09-14
IPC: H04L27/26
CPC classification number: H04L27/2628
Abstract: PURPOSE: A transmission device and a method are provided to use an unused band of a user through the other user using a cognitive radio communication by reducing an interference of a band which does not use. CONSTITUTION: A modulator(120) outputs a data symbol by modulating the data by a fixed modulation system. An interference control unit(130) assigns an interference eliminating carrier wave to a band out of effective band. The interference control unit decides a binary code capable of multiplying to the data symbol among the size of the interference eliminating carrier wave and a binary code combination. A binary code multiplying unit(140) respectively outputs the signal with multiplying the interference eliminating signal and the binary code to the data symbol. A reverse fast Fourier converter(150) generates an OFDM signal by converting the signal with multiplying the binary code to the data symbol and the interference eliminating signal to the reverse fast Fourier.
Abstract translation: 目的：提供一种传输设备和方法，通过减少不使用的频带的干扰，通过使用认知无线电通信的另一用户使用用户的未使用频带。 构成：调制器（120）通过固定调制系统调制数据来输出数据符号。 干扰控制单元（130）将干扰消除载波分配给有效频带之外的频带。 干扰控制单元决定能够与干扰消除载波的大小和二进制码组合之间的数据符号相乘的二进制码。 二进制码乘法单元（140）分别将干扰消除信号和二进制码乘以数据码元输出。 反向快速傅里叶变换器（150）通过将二进制码乘以数据符号的信号和干扰消除信号转换成反向快速傅立叶生成OFDM信号。
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