公开(公告)号：KR1020080074611A

公开(公告)日：2008-08-13

申请号：KR1020070013953

申请日：2007-02-09

Applicant: 삼성전자주식회사

Inventor： 한상근 ,  김성훈 ,  김정열

IPC: H01L23/62

CPC classification number: H01L23/5256 ,  H01L21/268 ,  H01L21/76897 ,  H01L21/78

Abstract: A semiconductor apparatus is provided to minimize a defect rate of a semiconductor memory apparatus by cutting a fuse with a laser or an electrical manner. A fuse unit includes a semiconductor substrate(10), a first fuse(F1), a first fuse formed on the first fuse, and a contact(C1) coupling the first fuse and a second fuse. An interlayer dielectric(20) is formed on the semiconductor substrate. The first fuse is formed on the interlayer dielectric. An inter-metal dielectric(30) having a contact hole is formed on the first fuse. The contact hole exposes a part of an upper surface of the first fuse. The contact coupling the first fuse to the second fuse is formed on the contact hole. The first fuse and the second fuse are serially connected by the contact. The second fuse is formed on the contact and the second interlayer dielectric. The second fuse is overlapped with the first fuse. A constant region of the second fuse is cut by a laser.

Abstract translation: 提供一种半导体装置，通过用激光或电气方式切割熔丝来最小化半导体存储装置的缺陷率。 熔丝单元包括半导体衬底（10），第一熔丝（F1），形成在第一熔丝上的第一熔丝以及将第一熔丝和第二熔丝耦合的触头（C1）。 在半导体衬底上形成层间电介质（20）。 第一个保险丝形成在层间电介质上。 在第一保险丝上形成具有接触孔的金属间电介质（30）。 接触孔暴露第一保险丝的上表面的一部分。 将第一保险丝耦合到第二保险丝的接触件形成在接触孔上。 第一个保险丝和第二个保险丝通过触点串联连接。 第二熔丝形成在触点和第二层间电介质上。 第二个保险丝与第一个保险丝重合。 第二个保险丝的恒定区域被激光切割。

公开(公告)号：KR1020070003296A

公开(公告)日：2007-01-05

申请号：KR1020050059171

申请日：2005-07-01

Applicant: 삼성전자주식회사

Inventor： 권혁준 ,  한상근 ,  김준호

IPC: G11C5/14 ,  G11C11/4074

Abstract: A memory device having a meshed VP line is provided to supply a cell capacitor plate voltage in order to prevent the influence from noise, by including VP lines with a meshed structure. In a memory device(300) including at least one cell array(310) including a plurality of cell blocks(315) including a plurality of cells and a peripheral circuit(320) generating an internal voltage and a control signal required for storing data in the cell array or reading the stored data, a first VP line(350) supplies a cell capacitor plate voltage of the cell array and is arranged in a first direction. A plurality of second VP lines(360-1~360-n) is arranged on the cell array in a second direction perpendicular to the first VP line, and is connected to the first VP line. A plurality of subsidiary VP lines(370-1~370-m) is arranged on the cell array in the first direction, and is connected to the second VP line.

Abstract translation: 提供具有网状VP线的存储器件，以通过包括具有网格结构的VP线来提供单元电容器板电压以便防止噪声的影响。 在包括包括多个单元的多个单元块（315）的至少一个单元阵列（310）的存储器件（300）和产生内部电压的外围电路（320）和用于存储数据所需的控制信号 单元阵列或读取存储的数据，第一VP线（350）提供单元阵列的单元电容器板电压并且布置在第一方向上。 多个第二VP线（360-1〜360-n）在与第一VP线垂直的第二方向上配置在单元阵列上，并与第一VP线连接。 多个辅助VP线（370-1〜370-m）沿第一方向布置在单元阵列上，并连接到第二VP线。