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公开(公告)号：KR101669989B1
公开(公告)日：2016-10-28
申请号：KR1020100049852
申请日：2010-05-27
Applicant: 삼성전자주식회사
CPC classification number: G06F11/1407 , G06F9/3857 , G06F9/3861 , G06F9/3867
Abstract: 이퀄모델상의제약조건을만족시키는파이프라인프로세서가제공된다. 제공되는파이프라인프로세서는적어도한 개의인스트럭션을다수의스테이지로나누어서처리하는파이프라인처리부및 파이프라인처리부내부의인스트럭션전부또는일부의처리결과를저장하고, 저장된처리결과를각각의인스트럭션의레이턴시를고려하여레지스터파일에기록하는이퀄모델보상부를포함할수 있다.
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4.发明公开
公开(公告)号：KR1020140034050A
公开(公告)日：2014-03-19
申请号：KR1020130096109
申请日：2013-08-13
Applicant: 삼성전자주식회사
Abstract: A time required for designing an assertion, verifying the designed assertion, and modifying the assertion due to architecture change of a verification target can be reduced by using assertion generating syntax included in a test program and automatically generating the assertion for the verification of a processor operation. [Reference numerals] (110) Input unit; (130) Assertion generating unit
Abstract translation: 可以通过使用包括在测试程序中的断言生成语法并自动生成用于验证处理器操作的断言来减少设计断言，验证设计的断言以及由于验证目标的体系结构改变而修改断言所需的时间 。 （附图标记）（110）输入单元; （130）断言产生单元
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公开(公告)号：KR1020140033616A
公开(公告)日：2014-03-19
申请号：KR1020120099609
申请日：2012-09-07
Applicant: 삼성전자주식회사
CPC classification number: G06F11/3624 , G06F8/41 , G06F11/3612 , G06F11/3672
Abstract: Disclosed are an apparatus and method for detecting a source code error location in a mixed-mode program, capable of providing source level debugging information without applying complex algorithm. An apparatus for detecting a source code error location in a mixed-mode program according to an embodiment comprises: a compiler unit which generates a first program by compiling a source code in a first mode, and generates a second program by compiling the source code in a second mode; a mapping table generation unit which generates a first mapping table for the first program, and a second mapping table for the second program; a simulation unit which simulates the first program and simulates the second program; a low-level data extraction unit which extracts first low-level data on the first program during the simulation of the first program, and extracts second low-level data on the second program during the simulation of the second program; a comparison data generation unit which maps the first low-level data onto the first mapping table to generate a verification target mapping table, and maps the second low-level data onto the second mapping table to generate a reference mapping table; and an error location detection unit which compares the verification target mapping table with the reference mapping table to determine whether there is an inconsistent record of data, and if so, obtains program location information relating to the record. [Reference numerals] (AA) Start; (BB) End; (S100) Compile step; (S110) Simulation and low level data extraction step; (S120) Comparison data generation step; (S130) Error location detection step
Abstract translation: 公开了一种用于检测混合模式程序中的源代码错误位置的装置和方法，能够提供源级调试信息而不应用复杂算法。 根据实施例的用于检测混合模式程序中的源代码错误位置的装置包括：编译单元，其通过以第一模式编译源代码来生成第一程序，并且通过将源代码编译成 第二种模式; 生成第一程序的第一映射表和第二程序的第二映射表的映射表生成单元， 模拟单元，其模拟第一程序并模拟第二程序; 低级数据提取单元，其在第一程序的模拟期间提取第一程序的第一低级数据，并且在第二程序的模拟期间提取关于第二程序的第二低级数据; 比较数据生成单元，将第一低级数据映射到第一映射表上，生成验证对象映射表，将第二低级数据映射到第二映射表，生成参照映射表; 以及错误位置检测单元，其将验证目标映射表与参考映射表进行比较，以确定是否存在不一致的数据记录，如果是，则获得与记录相关的节目位置信息。 （附图标记）（AA）开始; （BB）结束; （S100）编译步骤; （S110）模拟和低电平数据提取步骤; （S120）比较数据生成步骤; （S130）错误位置检测步骤
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Patent Agency Ranking
公开(公告)号：KR1020110130284A
公开(公告)日：2011-12-05
申请号：KR1020100049852
申请日：2010-05-27
Applicant: 삼성전자주식회사
CPC classification number: G06F11/1407 , G06F9/3857 , G06F9/3861 , G06F9/3867 , G06F9/30079
Abstract: PURPOSE: A pipe line processor and equal model preservation method are provided to maintain an equal model by processing the event of a pipe line. CONSTITUTION: A pipe line processor(101) processes an instruction by separating the instruction to plural stages. An equal model correction unit(102) stores the processing result of the instruction which is located in the inner side of the pipe line processing unit. The equal model correction unit records the processing result in a register file(103) considering of the latency of the instruction. The equal model correction unit records the processing result in the register file by responding to a recovery signal which restarts the pipe line processing unit.
Abstract translation: 目的：提供管道处理器和等效模型保存方法，通过处理管道事件来维持相等的模型。 构成：管线处理器（101）通过将指令分离成多级来处理指令。 相等模型校正单元（102）存储位于管线处理单元的内侧的指令的处理结果。 考虑到指令的等待时间，等模型校正单元将处理结果记录在寄存器文件（103）中。 相等模型校正单元通过响应重启管线处理单元的恢复信号将处理结果记录在寄存器文件中。
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公开(公告)号：KR1020110114240A
公开(公告)日：2011-10-19
申请号：KR1020100033774
申请日：2010-04-13
Applicant: 삼성전자주식회사
IPC: G06F15/163 , G06F13/14 , G06F9/28 , G06F13/38
CPC classification number: G06F15/17343 , G06F12/0806
Abstract: 멀티 코어 시스템에서 코어 간의 연결을 재구성가능하도록 하는 데이터 전송 장치 및 방법이 제공된다. 멀티 코어들 사이의 데이터를 전송하는 장치는, 멀티 코어로부터 수신된 프로그램 카운터를 이용하여 멀티 코어들 사이의 로컬 네트워크 연결을 나타내는 구성 정보를 생성하는 구성 정보 생성부와, 구성 정보에 따라서 멀티 코어들 사이의 데이터 전송 경로를 변경하는 적어도 하나의 스위칭부를 포함한다.
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公开(公告)号：KR101647818B1
公开(公告)日：2016-08-12
申请号：KR1020100033774
申请日：2010-04-13
Applicant: 삼성전자주식회사
IPC: G06F15/163 , G06F13/14 , G06F9/28 , G06F13/38
CPC classification number: G06F15/17343 , G06F12/0806
Abstract: 멀티코어시스템에서코어간의연결을재구성가능하도록하는데이터전송장치및 방법이제공된다. 멀티코어들사이의데이터를전송하는장치는, 멀티코어로부터수신된프로그램카운터를이용하여멀티코어들사이의로컬네트워크연결을나타내는구성정보를생성하는구성정보생성부와, 구성정보에따라서멀티코어들사이의데이터전송경로를변경하는적어도하나의스위칭부를포함한다.
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公开(公告)号：KR1020130105183A
公开(公告)日：2013-09-25
申请号：KR1020120027401
申请日：2012-03-16
Applicant: 삼성전자주식회사
CPC classification number: G06F11/3604 , G06F8/4452 , G06F11/3664 , G06F17/5027
Abstract: PURPOSE: Verification support device and method are provided to improve the verification accuracy and performance by masking invalid operation mapped in prologue and epilogue of a loop by modulo scheduling of a coarse grained array (CGA) based processor. CONSTITUTION: An invalid operation judgment unit (110) judges invalid operation from a source code scheduling result. A masking hint generation unit (120) generates a masking hint for invalid operation. The invalid operation is operation mapped in a prologue or an epilogue of a loop according to modulo scheduling of a compiler. A reconfigurable processor is a CGA based processor. A masking hint (121) includes ID information of a functional unit in which cycle number and invalid operation are mapped from the prologue or the epilogue. [Reference numerals] (110) Invalid operation judgment unit; (120) Masking hint generation unit; (121) Hint; (201) Scheduling result
Abstract translation: 目的：提供验证支持设备和方法，以通过基于粗粒度阵列（CGA）的处理器的模调度来掩蔽映射到循环序列和结尾的无效操作来提高验证精度和性能。 构成：无效操作判断单元（110）根据源代码调度结果判断无效操作。 屏蔽提示生成单元（120）生成用于无效操作的屏蔽提示。 根据编译器的模调度，无效操作是在循环的序言或结尾进行映射的操作。 可重构处理器是基于CGA的处理器。 掩蔽提示（121）包括从序列或结尾映射循环次数和无效操作的功能单元的ID信息。 （附图标记）（110）无效操作判断单元; （120）屏蔽提示生成单元; （121）提示; （201）调度结果
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