公开(公告)号：KR1020110027939A

公开(公告)日：2011-03-17

申请号：KR1020090085772

申请日：2009-09-11

Applicant: 삼성전자주식회사

Inventor： 장상환 ,  허성무 ,  유광석 ,  이영택 ,  조우영

IPC: G11C13/02 ,  G11C16/34 ,  G11C16/10

CPC classification number: G11C13/0004 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0057 ,  G11C2013/0092 ,  G11C2213/56

Abstract: PURPOSE: A PRAM memory device, a memory system having the same, and a method of a programming PRAM memory device are provided to increase program efficiency by adjusting the number of applying a verification pulse and the interval of thereof. CONSTITUTION: In an PRAM memory device, a memory system having the same, and a method of a programming PRAM memory device, a write pulse is applied to phase-change memory cells. Write data is programmed in phase-change memory cells(S110) At least one verification pulse is applied to the phase-change memory cells. It is determined whether a phase-change memory cells is programmed or not(S120).

Abstract translation: 目的：提供PRAM存储器件，具有该存储器件的存储器系统和编程PRAM存储器件的方法，以通过调整施加验证脉冲的数量及其间隔来提高程序效率。 构成：在PRAM存储器件中，具有相同存储器的存储器系统和编程PRAM存储器件的方法将写入脉冲施加到相变存储器单元。 写入数据被编程在相变存储器单元中（S110）至少一个验证脉冲被施加到相变存储器单元。 确定相变存储单元是否被编程（S120）。

公开(公告)号：KR1020110024147A

公开(公告)日：2011-03-09

申请号：KR1020090082030

申请日：2009-09-01

Applicant: 삼성전자주식회사

Inventor： 허성무 ,  장상환

IPC: G06F13/16 ,  G06F12/00 ,  G06F9/00

CPC classification number: G11C13/0004 ,  G06F12/0868 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069

Abstract: PURPOSE: A memory system is provided to increase operation speed by reducing the influence of a resistance drift of a resistance memory device and read out program information from a cache memory while programming data in a PRAM in a program mode. CONSTITUTION: A host(110) writes first data in a PRAM(Phase Change Random Access Memory)(150). The host writes program information about the first data in a cache memory(140). The host reads out the program information about the first data from the cache memory instead of reading out the first data from the resistance memory device in program-to-active time.

Abstract translation: 目的：提供一种存储器系统，通过减少电阻存储器件的电阻漂移的影响来提高操作速度，并在程序模式中编程PRAM中的数据时从高速缓冲存储器读出程序信息。 构成：主机（110）将第一数据写入PRAM（相变随机存取存储器）（150）。 主机将关于第一数据的程序信息写入缓存存储器（140）。 主机从缓存存储器中读出有关第一数据的程序信息，而不是从程序到活动时间从电阻存储器件读出第一数据。