中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

5 records (took 0.017 seconds)

    ＬＳＭ이 가능한 3차원 적층형 낸드 플래시 메모리 어레이 및 그 동작방법
    2.
    发明公开
    ＬＳＭ이 가능한 3차원 적층형 낸드 플래시 메모리 어레이 및 그 동작방법 有权
    3D堆叠NAND闪存存储器阵列启用LSM及其操作方法

    公开(公告)号：KR1020130097592A

    公开(公告)日：2013-09-03

    申请号：KR1020120019349

    申请日：2012-02-24

    Applicant: 서울대학교산학협력단

    Inventor： 박병국 ,  김완동

    IPC: G11C16/02 ,  H01L27/115 ,  H01L21/8247

    CPC classification number: G11C11/40 ,  G11C5/02 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/10 ,  G11C2213/71 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/792 ,  H01L27/2463 ,  H01L27/2481

    Abstract: PURPOSE: A 3D stacked NAND flash memory array capable of layer selection by multi-level operation (LSM) and an operating method thereof improve the degree of integration of the memory array by minimizing the increase in the number of string selection lines (SSL) for layer selection even when the number of layers of a vertically laminated active line is increased. CONSTITUTION: Multiple active lines are separated from multiple semiconductor layers (1st layer, 2nd layer, 3rd layer, 4th layer) in a first horizontal direction vertically laminated across an insulating film on a substrate. Multiple word lines are separated from the semiconductor layers in a second direction across an insulating film layer to be perpendicular to each active line. Multiple string selection lines (1st SSL,2nd SSL) are separated from the multiple semiconductor layers in the second direction across the insulating film layer and in parallel to each word line at one side of the multiple word lines.

    Abstract translation: 目的：能够通过多级操作（LSM）进行层选择的3D堆叠NAND闪速存储器阵列及其操作方法通过最小化字符串选择线（SSL）的数量的增加来提高存储器阵列的集成度， 即使当垂直层叠的有源线的层数增加时，也可以进行层选择。 构成：在垂直层叠在基板上的绝缘膜上的第一水平方向上，多个有源线与多个半导体层（第一层，第二层，第三层，第四层）分离。 多个字线在跨越绝缘膜层的第二方向上与半导体层分离以垂直于每个有源线。 多个串选择线（第一SSL，第二SSL）在跨越绝缘膜层的第二方向上与多个半导体层分离，并且与多个字线的一侧上的每个字线平行。

    3차원 적층형 메모리 어레이의 컨택 형성 방법
    5.
    发明公开
    3차원 적층형 메모리 어레이의 컨택 형성 방법 有权
    3D堆叠存储阵列的联系过程方法

    公开(公告)号：KR1020130007200A

    公开(公告)日：2013-01-18

    申请号：KR1020110064318

    申请日：2011-06-30

    Applicant: 서울대학교산학협력단

    Inventor： 박병국 ,  김완동 ,  김윤

    IPC: H01L21/8247 ,  H01L27/115

    CPC classification number: H01L27/2481 ,  H01L21/76897 ,  H01L27/0688 ,  H01L27/2463

    Abstract: PURPOSE: A method for forming a contact of a 3D laminate memory array is provided to reduce processing costs and steps by forming step type contacts with different depths once regardless of the number of layers. CONSTITUTION: A plurality of semiconductor layers(10) with a step protrusion part are formed on a substrate. A first hard mask material layer is formed on a first interlayer dielectric layer. A plurality of contact hole patterns(32) are formed by etching the first hard mask material layer. A second interlayer dielectric layer fills the plurality of contact hole patterns. A second hard mask material layer is deposited on the front side of the substrate. A plurality of contact holes(70) are formed by anisotropically etching the first and second interlayer dielectric layers.

    Abstract translation: 目的：提供一种用于形成3D层压存储器阵列的接触的方法，以便不管层数如何，通过形成具有不同深度的阶梯型接触来降低加工成本和步骤。 构成：在基板上形成具有台阶突出部的多个半导体层（10）。 第一硬掩模材料层形成在第一层间介质层上。 通过蚀刻第一硬掩模材料层形成多个接触孔图案（32）。 第二层间介电层填充多个接触孔图案。 第二硬掩模材料层沉积在基板的正面上。 通过各向异性蚀刻第一和第二层间电介质层形成多个接触孔（70）。

Patent Agency Ranking