公开(公告)号：KR101124860B1

公开(公告)日：2012-03-27

申请号：KR1020100102338

申请日：2010-10-20

Applicant: 성균관대학교산학협력단

Inventor： 김종태 ,  김경훈 ,  권순규

IPC: G06F11/10 ,  G06F12/00

Abstract: PURPOSE: A memory access method is provided to easily detect second memory error in case data is combined with parity bit and access a second memory. CONSTITUTION: Data is stored in a first memory. A parity bit is allocated to row lines of the data. Interleaving cells are divided in a second memory in which data and parity bit of the first memory are accessed. If interleaving cells are displayed on a coordinate, a parity cell is set in the interleaving cells having the same coordinate values. The parity bits of the first memory are allocated in the parity cell of the second memory.

Abstract translation: 目的：提供存储器访问方法，以便在数据与奇偶校验位组合并访问第二存储器的情况下容易地检测第二存储器错误。 规定：数据存储在第一个存储器中。 奇偶校验位分配给数据的行行。 交织单元被划分在其中访问第一存储器的数据和奇偶校验位的第二存储器中。 如果在坐标上显示交织单元，则在具有相同坐标值的交织单元中设置奇偶校验单元。 第一存储器的奇偶校验位被分配在第二存储器的奇偶校验单元中。