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公开(公告)号：KR102213026B1
公开(公告)日：2021-02-08
申请号：KR1020190066408
申请日：2019-06-05
Applicant: 성균관대학교산학협력단
Abstract: 본발명은박막의기계및 전기물성고속측정시스템에관한것으로서, 시편이안착되는시편고정대; 상기시편고정대의상부에형성되며시편에대한시험을수행하는측정부; 상기시편고정대에대한상기측정부의상대적인위치를 x축, y축및 z축방향으로변화시키는이동모듈; 및상기측정부와상기이동모듈을제어하는제어부;를포함하여이루어지며, 상기측정부는상기이동모듈에고정되는몸체부와상기몸체부에탈착가능하게고정되는측정프로브를구비하는것을특징으로한다. 이에따라, 다수미소재료의물성을정확하게측정하는것이가능한박막의기계및 전기물성고속측정시스템에관한것이다.
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公开(公告)号：KR101124860B1
公开(公告)日：2012-03-27
申请号：KR1020100102338
申请日：2010-10-20
Applicant: 성균관대학교산학협력단
Abstract: PURPOSE: A memory access method is provided to easily detect second memory error in case data is combined with parity bit and access a second memory. CONSTITUTION: Data is stored in a first memory. A parity bit is allocated to row lines of the data. Interleaving cells are divided in a second memory in which data and parity bit of the first memory are accessed. If interleaving cells are displayed on a coordinate, a parity cell is set in the interleaving cells having the same coordinate values. The parity bits of the first memory are allocated in the parity cell of the second memory.
Abstract translation: 目的：提供存储器访问方法，以便在数据与奇偶校验位组合并访问第二存储器的情况下容易地检测第二存储器错误。 规定：数据存储在第一个存储器中。 奇偶校验位分配给数据的行行。 交织单元被划分在其中访问第一存储器的数据和奇偶校验位的第二存储器中。 如果在坐标上显示交织单元，则在具有相同坐标值的交织单元中设置奇偶校验单元。 第一存储器的奇偶校验位被分配在第二存储器的奇偶校验单元中。
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公开(公告)号：KR1020200140418A
公开(公告)日：2020-12-16
申请号：KR1020190066408
申请日：2019-06-05
Applicant: 성균관대학교산학협력단
Abstract: 본발명은박막의기계및 전기물성고속측정시스템에관한것으로서, 시편이안착되는시편고정대; 상기시편고정대의상부에형성되며시편에대한시험을수행하는측정부; 상기시편고정대에대한상기측정부의상대적인위치를 x축, y축및 z축방향으로변화시키는이동모듈; 및상기측정부와상기이동모듈을제어하는제어부;를포함하여이루어지며, 상기측정부는상기이동모듈에고정되는몸체부와상기몸체부에탈착가능하게고정되는측정프로브를구비하는것을특징으로한다. 이에따라, 다수미소재료의물성을정확하게측정하는것이가능한박막의기계및 전기물성고속측정시스템에관한것이다.
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