公开(公告)号：KR101264877B1

公开(公告)日：2013-05-15

申请号：KR1020100077669

申请日：2010-08-12

Applicant: 재단법인대구경북과학기술원

Inventor： 최호진 ,  장환수 ,  김재현 ,  백성호 ,  김성빈 ,  오병윤

IPC: H01L21/306

Abstract: 실리콘웨이퍼위에마스크층을패터닝하는단계; 상기마스크층으로덮이지않은상기실리콘웨이퍼의일부를금속촉매화학적식각하는단계; 상기금속촉매화학적식각이후상기실리콘웨이퍼로부터잔존금속을제거하는단계; 상기잔존금속제거이후상기마스크층을제거하여에치피트가형성된실리콘웨이퍼를얻는단계; 및상기에치피트가형성된상기실리콘웨이퍼를전기화학적식각처리하여실리콘와이어어레이를형성하는단계를포함하는실리콘와이어구조체의제조방법이제공된다.

公开(公告)号：KR1020120015512A

公开(公告)日：2012-02-22

申请号：KR1020100077669

申请日：2010-08-12

Applicant: 재단법인대구경북과학기술원

Inventor： 최호진 ,  장환수 ,  김재현 ,  백성호 ,  김성빈 ,  오병윤

IPC: H01L21/306

CPC classification number: H01L21/02019 ,  H01L31/02363

Abstract: PURPOSE: A method for manufacturing a silicon wire structure is provided to reduce a width of a silicon wire by forming a plurality of etch pits in a region of the same area. CONSTITUTION: A mask layer is patterned on a silicon wafer(S1). A part of the silicon wafer, which is not covered with the mask layer, is chemically etched with a metallic catalyst(S2). Residual metal is removed from the silicon wafer after chemical etching with the metallic catalyst(S3). The silicon wafer including an etch pit is formed by eliminating the mask layer(S4). A silicon wire array is formed by electrochemically etching silicon wafer including the etch pit(S5).

Abstract translation: 目的：提供一种制造硅线结构的方法，通过在相同区域的区域中形成多个蚀刻凹坑来减小硅线的宽度。 构成：在硅晶片上形成掩模层（S1）。 未被掩模层覆盖的硅晶片的一部分用金属催化剂进行化学蚀刻（S2）。 用金属催化剂进行化学蚀刻后，从硅晶片除去残余金属（S3）。 通过消除掩模层形成包括蚀刻坑的硅晶片（S4）。 通过电化学蚀刻包括蚀刻坑的硅晶片形成硅线阵列（S5）。