Abstract:
PURPOSE: A silicon solar cell and a manufacturing method thereof are provided to remarkably reduce reflectivity by reducing light entered from outside through surface texturing to be re-reflected. CONSTITUTION: An emitter layer of conductive type which is opposite to a silicon substrate is formed on the silicon substrate(S210). A self-assembled monolayer film of a colloidal particle is formed on the emitter layer(S220). The surface of the emitter layer is textured by performing metallic catalyst chemical etching by using the self-assembled monolayer film as a mask(S230). A metal particle and the self-assembled monolayer film remaining after metallic catalyst chemical etching are eliminated(S240). [Reference numerals] (AA) Start; (BB) End; (S210) An emitter layer of opposite conductive type is formed on a silicon substrate; (S220) A self-assembled monolayer film of a colloidal particle is formed on the emitter layer; (S230) Metallic catalyst chemical etching is performed; (S240) A remaining metal particle and the self-assembled monolayer film are eliminated
Abstract:
본 명세서에서는 비구면 형태의 실리콘 몰드, 마이크로 렌즈 어레이 및 상기 실리콘 몰드와 마이크로 렌즈 어레이를 제조하는 방법을 제공한다. 본 명세서의 일 실시예에 따른 비구면 형태의 실리콘 몰드를 제조하는 방법은 기판의 일면에 산화막을 증착하고, 상기 증착한 산화막에 포토 레지스트를 도포하는 단계, 상기 도포된 포토 레지스트에 소정의 간격을 가지도록 패터닝하여 포토 레지스트 마스크를 형성하는 단계, 상기 패터닝된 포토 레지스트 마스크에 대하여 소정의 전해질 용액으로 에칭하는 단계, 및 상기 에칭이 완료된 기판의 산화막을 제거하는 단계를 포함하며, 상기 전해질 용액은 HF와 DMSO가 포함되어 있는 것을 특징으로 한다.
Abstract:
PURPOSE: A solar cell using a wire array and a manufacturing method thereof are provided to improve the efficiency of the solar cell at a wide temperature range by preventing the recombination of carriers at low and high temperatures by minimizing a moving distance of minority carriers. CONSTITUTION: A substrate(300) and a wire(312) are formed on a wire array. A transparent electrode layer(320) is formed on the surface of the wire array. A filling layer(330) made of insulation materials fills a space between wires with the transparent electrode layer. A top transparent electrode layer(340) is formed on the upper surface of the filling layer. A top electrode(350) is formed on the upper surface of the transparent electrode layer.
Abstract:
PURPOSE: A method of forming a multi-diameter silicon wire structure is provided to form a silicon wire having a wide surface area and high efficiency through metal-assisted catalytic etching. CONSTITUTION: An etching mask is patterned on the surface of a silicon substrate. The surface of silicon substrate, on which the etching mask is patterned, is chemically etched. A silicon wire whose longitudinal diameter changes is formed by successively changing one of any processing condition selected from a group consisting of the composition of an etching solution, etching time, and the temperature of the etching solution. A metallic catalyst is deposited on the surface of the silicon substrate.
Abstract:
하이브리드 태양전지 및 그 제조 방법이 개시된다. 본 개시의 일 실시 예로서, 서로 대향하는 두 전극 사이에 N형 실리콘 계 나노 구조체 및 P형 유기반도체가 혼합된 층 또는 P형 실리콘 계 나노 구조체 및 N형 유기반도체가 혼합된 층을 적어도 한 층 이상 포함하고 있는 하이브리드 태양전지가 제공된다.
Abstract:
PURPOSE: A method for manufacturing a silicon wire structure is provided to reduce a width of a silicon wire by forming a plurality of etch pits in a region of the same area. CONSTITUTION: A mask layer is patterned on a silicon wafer(S1). A part of the silicon wafer, which is not covered with the mask layer, is chemically etched with a metallic catalyst(S2). Residual metal is removed from the silicon wafer after chemical etching with the metallic catalyst(S3). The silicon wafer including an etch pit is formed by eliminating the mask layer(S4). A silicon wire array is formed by electrochemically etching silicon wafer including the etch pit(S5).
Abstract:
PURPOSE: A hybrid solar cell and a manufacturing method thereof are provided to improve low charge mobility and electrical conductivity of an organic semiconductor material by using an inorganic material. CONSTITUTION: A hybrid solar battery comprises a substrate(100), a transparent electrode(110), a buffer layer(120), a mixture layer(130A) including a silicon nano structure and an organic semiconductor, and an upper electrode(140). The transparent electrode is arranged on the substrate. The buffer layer can be formed on the transparent electrode(110). A mixed layer of an N type silicon-based nano structure and a P type organic semiconductor or a mixed layer of a P type silicon-based nano structure and an N type organic semiconductor is formed between the two facing electrodes.