公开(公告)号：KR100800507B1

公开(公告)日：2008-02-04

申请号：KR1020060135357

申请日：2006-12-27

Applicant: 재단법인서울대학교산학협력재단

Inventor： 박병국 ,  강상우

IPC: H01L29/775 ,  H01L21/336

CPC classification number: H01L29/7613 ,  H01L29/4983 ,  H01L29/66439

Abstract: A self-aligned single-electron transistor and a fabricating method thereof are provided to prevent generation of parasitic components of parallel MOSFETs by forming dual gates at both sides centering around a control gate without overlapping therewith. Source and drain regions(22a,24a) are formed on a semiconductor substrate to be separated from each other. A channel region is between the source and drain regions. A control gate(40b) is formed on the channel region. A gate dielectric(70) is formed on an upper portion of the channel region by surrounding the control gate. Two sidewall gates(80a,80b) are formed and self-aligned at both sides of an upper portion of the gate dielectric centering around the control gate. The source and drain regions are self-aligned at each sidewall gate. A dielectric sidewall spacer is formed along each sidewall gate on the source and drain regions.

Abstract translation: 提供自对准单电子晶体管及其制造方法，以通过在不与其重叠的情况下在围绕控制栅极的中心处的两侧形成双栅极来防止并联MOSFET的寄生元件的产生。 源极和漏极区域（22a，24a）形成在半导体衬底上以彼此分离。 沟道区域在源区和漏区之间。 控制栅极（40b）形成在沟道区上。 栅极电介质（70）通过围绕控制栅极而形成在沟道区的上部。 两个侧壁门（80a，80b）在围绕控制栅的中心栅电介质的上部两侧形成并自对准。 源极和漏极区域在每个侧壁栅极处是自对准的。 沿着源极和漏极区域上的每个侧壁栅极形成电介质侧壁间隔物。