公开(公告)号：KR100811997B1

公开(公告)日：2008-03-10

申请号：KR1020060121697

申请日：2006-12-04

Applicant: 삼성에스디아이 주식회사 ,  재단법인서울대학교산학협력재단 ,  한민구

Inventor： 한민구 ,  송인혁 ,  박중현

IPC: H01L29/786

CPC classification number: H01L29/78621 ,  H01L27/1248 ,  H01L29/78606

Abstract: A thin film transistor, a method for manufacturing the same, and a flat panel display including the same are provided to form a lightly doped drain structure in a junction part between an active region and source/drain regions by using a sidewall effect. A semiconductor layer(13) includes an active region, source/drain regions, and a lightly doped region. A gate insulating layer(14) and a gate electrode(15) are overlapped on the active region. A first interlayer dielectric(16) is formed on the source/drain regions and the gate electrode. A second interlayer dielectric(17) is formed on the first interlayer dielectric and includes a contact hole for exposing a part of the source/drain regions. Source/drain electrodes(18,19) are connected through the contact hole to the source/drain regions. The amount of the first interlayer dielectric deposited on a sidewall of the gate insulating layer is larger than the amount of the first interlayer dielectric deposited on the source/drain regions.

Abstract translation: 提供薄膜晶体管，其制造方法和包括该薄膜晶体管的平板显示器，以通过使用侧壁效应在有源区域和源极/漏极区域之间的接合部分中形成轻掺杂的漏极结构。 半导体层（13）包括有源区，源极/漏极区和轻掺杂区。 栅极绝缘层（14）和栅电极（15）重叠在有源区上。 在源极/漏极区域和栅极电极上形成第一层间电介质（16）。 第二层间电介质（17）形成在第一层间电介质上，并且包括用于暴露一部分源/漏区的接触孔。 源/漏电极（18,19）通过接触孔连接到源极/漏极区域。 沉积在栅极绝缘层的侧壁上的第一层间电介质的量大于沉积在源极/漏极区上的第一层间电介质的量。

公开(公告)号：KR1020030069779A

公开(公告)日：2003-08-27

申请号：KR1020020065467

申请日：2002-10-25

Applicant: 재단법인서울대학교산학협력재단

Inventor： 송인혁 ,  한민구 ,  김천홍

IPC: H01L29/786

CPC classification number: H01L29/66757 ,  H01L27/1281 ,  H01L29/78606 ,  H01L29/78675

Abstract: PURPOSE: A thin film transistor(TFT) and a fabricating method therefor are provided to form a polycrystalline silicon TFT having high mobility, a low leakage current and excellent electrical reliability regarding high temperature carrier stress by growing uniform grains not smaller than 4 micrometer so that one grain boundary is formed in a channel region. CONSTITUTION: An insulated substrate is prepared. A heat intercepting layer is disposed on the insulated substrate in a predetermined channel formation region, made of a material that has low heat conductivity to control vertical heat transfer in an annealing process. A semiconductor layer is formed on the insulated substrate and the heat intercepting layer, having a source region, a drain region and a channel region between the source region and the drain region such that the channel region overlaps the heat intercepting layer. An insulation layer is formed on the semiconductor layer in the channel region. A gate electrode is formed on the insulation layer, overlapping the channel region.

Abstract translation: 目的：提供薄膜晶体管（TFT）及其制造方法，以通过生长不小于4微米的均匀晶粒来形成具有高迁移率，低漏电流和低温载流子应力的优异电可靠性的多晶硅TFT， 在沟道区域形成一个晶界。 构成：准备绝缘基板。 热绝缘层设置在预定通道形成区域中的绝缘基板上，该材料由热导率低的材料制成，以在退火过程中控制垂直传热。 在绝缘基板和截流层上形成半导体层，该源极区域，漏极区域和源极区域与漏极区域之间的沟道区域，使得沟道区域与热拦截层重叠。 在沟道区域的半导体层上形成绝缘层。 在绝缘层上形成栅极电极，与沟道区域重叠。