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公开(公告)号:KR1020090088693A
公开(公告)日:2009-08-20
申请号:KR1020080014125
申请日:2008-02-15
Applicant: 재단법인서울대학교산학협력재단
IPC: H01L27/115 , H01L21/8247
CPC classification number: G11C8/14 , G11C16/0483 , H01L21/26586 , H01L27/11565 , H01L27/11568 , H01L27/11582 , H01L29/66833 , H01L21/28282 , H01L27/10882 , H01L27/1157 , H01L29/42352
Abstract: An NAND flash memory array, and a method for operating and manufacturing the same are provided to independently operate each cell by a cut-off gate by driving two cells by one word line. A plurality of silicon square pillars(14) has a fixed height in order to form a plurality of tranches on a silicon substrate. An insulation film square pillar(52) is positioned between bit lines. The bit lines are vertically formed about each trench direction. A plurality of cut-off gate lines is formed in a bottom side of each trench. A first insulation film is positioned between the cut-off gate lines. A second insulation film(80) is formed in an exposed part of each cut-off gate line and each silicon square pillar. A plurality of charge storage layers is formed on both sidewalls of each silicon square pillar. The second insulation film is positioned between the charge storage layers. A third insulation film(82) is formed on an exposed part of the second insulation film and a top part of each charge storage layer. A plurality of word lines(102) is formed on a top part of the third insulation film.
Abstract translation: 提供NAND闪存阵列及其操作和制造方法,以通过将两个单元驱动一个字线来通过截止门来独立地操作每个单元。 多个硅方形柱(14)具有固定的高度,以在硅衬底上形成多个阶段。 绝缘膜方柱(52)位于位线之间。 位线围绕每个沟槽方向垂直地形成。 在每个沟槽的底侧形成多个截止栅极线。 第一绝缘膜位于截止栅极线之间。 在每个截止栅极线和每个硅方柱的暴露部分中形成第二绝缘膜(80)。 在每个硅方柱的两个侧壁上形成多个电荷存储层。 第二绝缘膜位于电荷存储层之间。 在第二绝缘膜的暴露部分和每个电荷存储层的顶部上形成第三绝缘膜(82)。 多个字线(102)形成在第三绝缘膜的顶部。
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公开(公告)号:KR100966265B1
公开(公告)日:2010-06-28
申请号:KR1020080014125
申请日:2008-02-15
Applicant: 재단법인서울대학교산학협력재단
IPC: H01L27/115 , H01L21/8247
CPC classification number: G11C8/14 , G11C16/0483 , H01L21/26586 , H01L27/11565 , H01L27/11568 , H01L27/11582 , H01L29/66833
Abstract: 본 발명은 수직채널을 갖는 2개의 셀을 하나의 컨트롤 게이트(워드 라인)로 독립적으로 동작시키기 위하여 컨트롤 게이트 아래에 차단 게이트 라인을 갖는 낸드 플래시 메모리 어레이와 그 동작 및 제조방법에 관한 것으로, 종래 수직채널 구조보다 소요 면적을 현저히 줄일 수 있어 고집적화에 유리하고, 프로그램 동작시 공유하는 차단 게이트를 OFF시킴으로써 셀프 부스팅 효과로 반대편 셀에 프로그램되는 것을 막을 수 있고, 리드 동작시 공유하는 워드 라인(컨트롤 게이트)으로 전기적 차폐가 가능하여 반대편 셀의 저장 상태에 따른 영향을 극소화시킬 수 있는 효과 등이 있으며, 통상의 CMOS 공정으로도 제조 가능한 장점이 있다.
수직 채널, 차단 게이트, 낸드 플래시 메모리-
公开(公告)号:KR100777016B1
公开(公告)日:2007-11-16
申请号:KR1020060055596
申请日:2006-06-20
Applicant: 재단법인서울대학교산학협력재단
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L27/115 , H01L27/11521 , H01L27/11524 , H01L21/26513 , H01L21/76885 , H01L27/11568
Abstract: A NAND flash memory array having a pillar structure and a fabricating method of the same are provided to improve remarkably a degree of integration in comparison with a two-dimensional planar structure by reducing an area of a memory cell in half. One or more insulator strips(24) have a pillar shape protruded in a constant interval on a semiconductor substrate(10). One or more semiconductor strips(14) have a pillar shape protruded in parallel between the insulator strips. One or more trenches(34) are formed by using the insulator strips and the semiconductor strips. Two or three dielectric layers include charge trap layers(44) and are formed at both sidewalls and a bottom of each trench. A sidewall gate(50) is formed on the dielectric layers. A first source/drain region is formed on the semiconductor strip of the bottom of the each trench. A second source/drain region is formed at an upper part of a pillar protruded from each semiconductor strip.
Abstract translation: 提供具有柱结构的NAND快闪存储器阵列及其制造方法,通过将存储单元的面积减少一半,可以显着地提高与二维平面结构相比的集成度。 一个或多个绝缘体条(24)具有在半导体衬底(10)上以恒定间隔突出的柱形。 一个或多个半导体条(14)具有在绝缘体条之间平行突出的柱状。 通过使用绝缘体条和半导体条形成一个或多个沟槽(34)。 两个或三个电介质层包括电荷陷阱层(44),并形成在每个沟槽的两个侧壁和底部。 侧壁栅极(50)形成在电介质层上。 在每个沟槽的底部的半导体条上形成第一源极/漏极区域。 第二源极/漏极区域形成在从每个半导体条突出的柱的上部。
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