반도체 영역의 선택적 식각방법, 반도체층의 분리방법 및반도체소자를 기판으로부터 분리하는 방법
    1.
    发明授权
    반도체 영역의 선택적 식각방법, 반도체층의 분리방법 및반도체소자를 기판으로부터 분리하는 방법 有权
    选择半导体区域的方法,半导体层的分离方法和从衬底的半导体器件的分离方法

    公开(公告)号:KR100889978B1

    公开(公告)日:2009-03-25

    申请号:KR1020070103186

    申请日:2007-10-12

    Inventor: 류상완 박준모

    CPC classification number: H01L21/30635

    Abstract: A method of selectively etching semiconductor region, a separation method of a semiconductor layer and a separation method of a semiconductor device from a substrate are provided to easily separate the semiconductor structure and transfer to the other substrate by using the electrolytic etching manner. The first semiconductor layer(230) of the N-type GaN series, and the second semiconductor layer(240) of the other conductive type GaN series and a semiconductor element portion(300) are successively formed on the first substrate(210). The semiconductor element portion is adhered to the second substrate(500). The etching is performed by using the electrolyte including the oxalic acid. The etching rate of the first semiconductor layer is greater than the etching rate of the second semiconductor layer. The semiconductor layer is etched more quickly than the second semiconductor.

    Abstract translation: 提供了选择性地蚀刻半导体区域的方法,半导体层的分离方法和半导体器件与衬底的分离方法,以便通过使用电解蚀刻方式容易地分离半导体结构并转移到另一个衬底。 在第一基板(210)上依次形成N型GaN系列的第一半导体层(230)和另一导电型GaN系列的第二半导体层(240)和半导体元件部(300)。 半导体元件部分粘附到第二基板(500)。 通过使用包含草酸的电解质进行蚀刻。 第一半导体层的蚀刻速率大于第二半导体层的蚀刻速率。 半导体层比第二半导体蚀刻得更快。

    나노 구조물 및 그 제조방법
    2.
    发明授权
    나노 구조물 및 그 제조방법 失效
    纳米结构及其制造

    公开(公告)号:KR100823809B1

    公开(公告)日:2008-04-21

    申请号:KR1020060107913

    申请日:2006-11-02

    Inventor: 박준모 류상완

    CPC classification number: B82B1/008 B82B3/0038 B82Y40/00

    Abstract: A nano structure is provided to embody a more beautiful color than ordinary pigments, and be surface-colored at low cost and in a simple manner. A method for manufacturing a nano structure for coloring the surface thereof includes the steps of: forming a first metal layer on the upper part of the surface; anodizing the metal layer to form a nano hole array structure(20) in which nano holes are formed in an array shape at regular intervals; forming a second metal layer(30) on the at least upper parts of the nano holes; and further forming a protective layer on the upper part on which the second metal layer is formed. The pitch(D) between nano holes is 20-500 nm.

    Abstract translation: 提供纳米结构以体现比普通颜料更美丽的颜色,并以低成本和简单的方式进行表面着色。 制造用于使其表面着色的纳米结构的方法包括以下步骤:在表面的上部形成第一金属层; 阳极氧化金属层以形成纳米孔阵列结构(20),其中纳米孔以规则间隔形成为阵列形状; 在所述纳米孔的至少上部上形成第二金属层(30); 并在其上形成有第二金属层的上部形成保护层。 纳米孔之间的间距(D)为20-500nm。

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