公开(公告)号：KR101268996B1

公开(公告)日：2013-05-29

申请号：KR1020120021150

申请日：2012-02-29

Applicant: 조선대학교산학협력단

Inventor： 이정아 ,  소마순다람,나타르잔

IPC: G06F11/28 ,  G06F11/07 ,  G06F11/10

Abstract: PURPOSE: An error detection device based on SEDC(Scalable Error Detection Coding) for a programmable addition/subtraction operation unit and a self-checking programmable addition/subtraction operation unit which includes the error detection device are provided to enable an input SEDC generator and an error detector to generate and compare linear and flexible SEDC for input of various bits, thereby detecting errors in addition/subtraction operations. CONSTITUTION: An input SEDC generator(100) receives binary input data and a carry-in bit. The input SEDC generator generates input SEDC which includes carry-out input SEDC and sum-out input SEDC corresponding to kinds of addition/deduction operations. An error detector(120) receives carry-out data and sum-out data and generates output SEDC which includes carry-out output SEDC and the sum-out output SEDC. The error detector outputs an error detection result by determining identity of the carry-out output SEDC and the carry-out input SEDC.

Abstract translation: 目的：提供一种基于用于可编程加减运算单元的SEDC（可伸缩误差检测编码）和包括错误检测装置的自检可编程加减运算单元的错误检测装置，以使输入SEDC发生器和 误差检测器，用于生成和比较线性和灵活的SEDC，用于各种位的输入，从而检测加法/减法操作中的错误。 构成：输入SEDC发生器（100）接收二进制输入数据和进位位。 输入SEDC发生器产生输入SEDC，其包括对应于加法/扣除操作的种类的输入输入SEDC和总和输入SEDC。 误差检测器（120）接收进位数据和总和数据，并产生包括进位输出SEDC和总和输出SEDC的输出SEDC。 误差检测器通过确定进位输出SEDC和进位输出SEDC的识别来输出错误检测结果。

公开(公告)号：KR101297318B1

公开(公告)日：2013-08-16

申请号：KR1020120016622

申请日：2012-02-17

Applicant: 조선대학교산학협력단

Inventor： 이정아 ,  소마순다람,나타르잔

IPC: H03M13/00

CPC classification number: H03M13/615 ,  H03M13/01 ,  H03M13/6502

Abstract: PURPOSE: A scalable error detection coding (SEDC)-based error detection apparatus for a compare unit and a self-checking compare unit including the same are provided to detect errors in comparison computations. CONSTITUTION: An error detection apparatus (100) comprises a comparison output generator (110), an input error detection code generator (120), and an error detector (130). The comparison output generator encodes results of comparison of binary input data from a compare unit into 2-bit comparison result data. An input error detection code generator receives binary input data, and generates input error detection codes that are error detection code depending on the comparison result of the binary input data. The error detector receives the comparison result data and generates 2-bit output error detection codes that are error detection codes for the comparison result data. The error detector outputs an error detection result by determining whether the output error detection codes are identical to the input error detection codes.

Abstract translation: 目的：提供一种用于比较单元和包括该比较单元的自检比较单元的可扩展错误检测编码（SEDC）错误检测装置，用于检测比较计算中的错误。 构成：误差检测装置（100）包括比较输出发生器（110），输入错误检测码发生器（120）和误差检测器（130）。 比较输出发生器将来自比较单元的二进制输入数据的比较结果编码为2比较结果数据。 输入错误检测码发生器接收二进制输入数据，根据二进制输入数据的比较结果生成作为错误检测码的输入错误检测码。 误差检测器接收比较结果数据，并生成作为比较结果数据的错误检测码的2位输出错误检测码。 错误检测器通过确定输出错误检测码是否与输入错误检测码相同来输出错误检测结果。

公开(公告)号：KR101272620B1

公开(公告)日：2013-06-10

申请号：KR1020120023871

申请日：2012-03-08

Applicant: 조선대학교산학협력단

Inventor： 이정아 ,  소마순다람,나타르잔

IPC: G06F11/26 ,  G06F11/10

CPC classification number: G06F11/10

Abstract: PURPOSE: An error detecting device for a self diagnosis operation processing device based on expanded error detection codes and an operation processing system including an error detection device are provided to perform self diagnosis to a code generation error or an operation error of an operation processing circuit by generating an error detection signal. CONSTITUTION: A first EDC(Error Detection Coding) check circuit(100a) receives EDC and binary output data from an operation processing circuit and outputs a first error detection signal. A second EDC check circuit(100b) receives the EDC and the binary output data and outputs a second error detection signal. EDC check circuits output an error detection signal of one bit regardless of the length of the EDC and the output data and determine the error generation of the error detection code according to a combination of the first and the second error detection signals.

Abstract translation: 目的：提供一种用于基于扩展错误检测码的自诊断操作处理装置的错误检测装置和包括错误检测装置的操作处理系统，以通过以下操作来执行自诊断到运算处理电路的代码生成错误或操作错误： 产生错误检测信号。 构成：第一EDC（错误检测编码）检查电路（100a）从操作处理电路接收EDC和二进制输出数据，并输出第一错误检测信号。 第二EDC检查电路（100b）接收EDC和二进制输出数据并输出第二错误检测信号。 EDC检查电路输出一位错误检测信号，而不管EDC和输出数据的长度如何，并根据第一和第二错误检测信号的组合确定错误检测码的错误产生。

公开(公告)号：KR101268998B1

公开(公告)日：2013-05-29

申请号：KR1020120006065

申请日：2012-01-19

Applicant: 조선대학교산학협력단

Inventor： 이정아 ,  소마순다람,나타르잔

IPC: G06F11/10

Abstract: PURPOSE: An error detection device based on scalable error detection coding for a programmable shift/rotate operation unit and a self-checking programmable shift/rotate operation unit which includes the error detection device are provided to generate and compare linear flexible SEDC for input various bits, thereby detecting errors in a shift/rotate operation. CONSTITUTION: An input SEDC generator(110) receives binary input data and a shift bit and generates input SEDC corresponding to kinds of a shift/rotate operation. An error detector(120) receives binary output data and an input error detection code and generates output SEDC. The error detector outputs an error detection result by determining identity of the output SEDC and the input SEDC. An input error detection code generator includes a 2 bit SEDC truth table, which stores 2 bit SEDC, and an input SEDC generation unit which generates the input SEDC.

Abstract translation: 目的：提供一种基于可编程移位/旋转操作单元的可伸缩错误检测编码的错误检测装置和包括错误检测装置的自检可编程移位/旋转操作单元，用于生成和比较用于输入各种位的线性灵活SEDC ，从而检测换档/旋转操作中的错误。 构成：输入SEDC发生器（110）接收二进制输入数据和移位位，并产生对应于移位/旋转操作的种类的输入SEDC。 误差检测器（120）接收二进制输出数据和输入错误检测码并产生输出SEDC。 误差检测器通过确定输出SEDC和输入SEDC的标识来输出错误检测结果。 输入错误检测码发生器包括存储2位SEDC的2位SEDC真值表和生成输入SEDC的输入SEDC生成单元。

公开(公告)号：KR101268997B1

公开(公告)日：2013-05-29

申请号：KR1020120002924

申请日：2012-01-10

Applicant: 조선대학교산학협력단

Inventor： 이정아 ,  소마순다람,나타르잔

IPC: G06F11/26 ,  G06F11/10

Abstract: PURPOSE: An error detection device based on SEDC(Scalable Error Detection Coding) for a programmable Boolean operation unit and a self-checking programmable Boolean operation unit which includes the error detection device are provided to separately perform generation of SEDC from input data, thereby implementing a combination approval system without decreasing speed of a Boolean operation or deteriorating performance of latency. CONSTITUTION: An input SEDC generator(110) receives binary input data and generates input SEDC corresponding to kinds of a Boolean operation. An error detector(120) receives the binary output data and the input SEDC and generates output SEDC. The error detector outputs an error detection result by determining identity of the output SEDC and the input SEDC. The input SEDC generator includes a 2 bit input SEDC generation unit which generates the 2 bit input SEDC as the input SEDC.

Abstract translation: 目的：提供一种基于用于可编程布尔运算单元的SEDC（可伸缩误差检测编码）和包括错误检测装置的自检可编程布尔运算单元的错误检测装置，以分别从输入数据执行SEDC的生成，从而实现 组合审批系统，而不会降低布尔运算速度或降低延迟性能。 构成：输入SEDC发生器（110）接收二进制输入数据并生成与布尔运算种类对应的输入SEDC。 误差检测器（120）接收二进制输出数据和输入SEDC并产生输出SEDC。 误差检测器通过确定输出SEDC和输入SEDC的标识来输出错误检测结果。 输入SEDC发生器包括2位输入SEDC生成单元，其生成作为输入SEDC的2位输入SEDC。

公开(公告)号：KR101267894B1

公开(公告)日：2013-05-27

申请号：KR1020110098730

申请日：2011-09-29

Applicant: 조선대학교산학협력단

Inventor： 이정아 ,  소마순다람,나타르잔 ,  이정근

IPC: G06F11/10

Abstract: 본발명은확장형오류검출코드생성기, 그생성기를구비한자가검사룩업테이블및 확장형오류검출코드생성방법에관한것으로, 보다구체적으로는서로다른길이의이진입력데이터에대해오류검출코드를생성하는복수개의오류검출코드생성수단을구비하여, 상기오류검출코드생성수단들단독또는조합에의해오류검출코드의길이를유동적으로확장할수 있어, 최소한의하드웨어추가로이진입력데이터전체의단방향오류를검출할수 있는확장형오류검출코드생성기와오류검출코드생성방법그리고상기확장형오류검출코드생성기를구비하여 LUT데이터전체를자가검사하거나매 동작시 LUT데이터를자가검사할수 있는자가검사룩업테이블에관한것이다.

公开(公告)号：KR1020130034713A

公开(公告)日：2013-04-08

申请号：KR1020110098730

申请日：2011-09-29

Applicant: 조선대학교산학협력단

Inventor： 이정아 ,  소마순다람,나타르잔 ,  이정근

IPC: G06F11/10

Abstract: PURPOSE: An SEDC(Scalable Error Detection Coding) generator, a lookup table including the SEDC generator, and an SEDC generation method are provided to generate SEDC for a lookup table data of in a length direction, thereby performing a unidirectional error check for the entire lookup table data. CONSTITUTION: A code length calculation module calculates the length of SEDC which is generated for binary input data. An SEDC generation module(100) includes a 2 bit input SEDC generation unit(110), a 3 bit input SEDC generation unit(120), or a 4 bit input SEDC generation unit. The SEDC generation module generates SEDC of a calculated length by an individual or a combination of the SEDC generation units.

Abstract translation: 目的：提供SEDC（可伸缩错误检测编码）生成器，包括SEDC生成器的查找表和SEDC生成方法，以生成用于长度方向的查找表数据的SEDC，从而对整个步骤执行单向错误检查 查找表数据。 构成：代码长度计算模块计算为二进制输入数据生成的SEDC的长度。 SEDC生成模块（100）包括2位输入SEDC生成单元（110），3位输入SEDC生成单元（120）或4位输入SEDC生成单元。 SEDC生成模块通过个体或SEDC生成单元的组合生成计算出的长度的SEDC。