公开(公告)号：KR1020040011916A

公开(公告)日：2004-02-11

申请号：KR1020020045232

申请日：2002-07-31

Applicant: 학교법인연세대학교

Inventor： 정웅 ,  정종철 ,  박우찬 ,  이문기 ,  한탁돈

IPC: G06F7/52

CPC classification number: G06F7/535 ,  G06F2207/5354

Abstract: PURPOSE: A pipelined ALU(Arithmetic and Logical Unit) having a lookup table of a small size and an operation method thereof are provided to decrease the size of the lookup table while increasing a delay time by one cycle. CONSTITUTION: A dividend X and a divisor Y have a regulated fixed point. The lookup table(LUT2) stores internal parameters and calculates the 1/(Yh)¬2 by using the divisor. The first multiplier(MUL3) calculates the divisor A by multiplying the 1/(Yh)¬2 of the lookup table to the (Yh-Y1) obtained from the dividend X and the divisor Y. The second and the third multiplier(MUL4,MUL5) calculate and output the AX and the AY by respectively operating the divisor A to the dividend Y and the divisor Y. The fourth multiplier(MUL6) outputs a quotient Q by operating the AX to the bit-inverted 2-AY.

Abstract translation: 目的：提供具有小尺寸查找表及其操作方法的流水线ALU（算术和逻辑单元），以减小查找表的大小，同时将延迟时间增加一个周期。 构成：股息X和除数Y具有规定的固定点。 查找表（LUT2）存储内部参数，并使用除数计算1 /（Yh）¬2。 第一乘法器（MUL3）通过将查找表的1 /（Yh）¬2与从被除数X和除数Y获得的（Yh-Y1）相乘来计算除数A.第二和第三乘法器（MUL4， MUL5）通过将除数A分配到除数Y和除数Y来计算和输出AX和AY。第四乘法器（MUL6）通过将AX操作到位反转的2-AY来输出商Q。

公开(公告)号：KR100433131B1

公开(公告)日：2004-05-28

申请号：KR1020020045232

申请日：2002-07-31

Applicant: 학교법인연세대학교

Inventor： 정웅 ,  정종철 ,  박우찬 ,  이문기 ,  한탁돈

IPC: G06F7/52

CPC classification number: G06F7/535 ,  G06F2207/5354

Abstract: A pipelined divider with a small lookup table is disclosed. The pipelined divider can greatly reduce the size of a lookup table with a low cost to overcome the problems involved in the conventional pipelined divider requiring a large lookup table due to its iterative operation type. The pipelined divider has a delay time of 3 cycles in a single precision, and can reduce a chip size by about 1/3 in comparison to the existing pipelined divider.

Abstract translation: 公开了一种带有小查找表的流水线分隔器。 流水线分隔器可以以低成本大大减小查找表的大小，以克服由于其迭代操作类型而需要大型查找表的传统流水线分隔器中涉及的问题。 流水线式分频器的延迟时间为3个周期，单一精度，与现有流水线分频器相比，可将芯片尺寸缩小约1/3。