公开(公告)号：KR100441080B1

公开(公告)日：2004-07-21

申请号：KR1020020045234

申请日：2002-07-31

Applicant: 학교법인연세대학교

Inventor： 이길환 ,  박우찬 ,  김일산 ,  한탁돈 ,  김신덕

IPC: G06T17/00

Abstract: PURPOSE: An operation method of a pixel cache structure in a three-dimensional graphic accelerator is provided to reduce cache pollution by loading only data with the high probability of being reused, thereby increasing a cache success rate. CONSTITUTION: Information of the existing fragment having the same texture coordinates as a newly inputted segment are detected from a pixel cache(421) and an NT(Non-Temporal) buffer(422). A depth value of the newly inputted fragment is compared with a depth value of the existing fragment. If the depth value of the newly inputted fragment is larger than the depth value of the existing fragment, information of the newly inputted fragment is stored in the NT buffer. If the depth value of the newly inputted fragment is smaller than the depth value of the existing fragment, the information of the newly inputted fragment is stored in the pixel cache. A color reading unit(413) executes a read operation of a color value of the newly inputted fragment. An alpha mixing unit(415) executes alpha mixing to the read color value and a color value mixed in a texture mixing unit(403). A color write unit(417) stores the alpha-mixed color value in the pixel cache.

Abstract translation: 目的：提供一种三维图形加速器中像素缓存结构的操作方法，通过仅加载重用概率高的数据来降低缓存污染，从而提高缓存成功率。 构成：从像素高速缓冲存储器（421）和NT（Non-Temporal）缓冲器（422）检测具有与新输入的段相同的纹理坐标的现有片段的信息。 将新输入的片段的深度值与现有片段的深度值进行比较。 如果新输入的片段的深度值大于现有片段的深度值，则将新输入的片段的信息存储在NT缓冲器中。 如果新输入的片段的深度值小于现有片段的深度值，则将新输入的片段的信息存储在像素高速缓存中。 彩色读取单元（413）执行新输入的片段的颜色值的读取操作。 阿尔法混合单元（415）对读取的颜色值和在纹理混合单元（403）中混合的颜色值执行阿尔法混合。 颜色写入单元（417）将阿尔法混合的颜色值存储在像素高速缓存中。

公开(公告)号：KR100433131B1

公开(公告)日：2004-05-28

申请号：KR1020020045232

申请日：2002-07-31

Applicant: 학교법인연세대학교

Inventor： 정웅 ,  정종철 ,  박우찬 ,  이문기 ,  한탁돈

IPC: G06F7/52

CPC classification number: G06F7/535 ,  G06F2207/5354

Abstract: A pipelined divider with a small lookup table is disclosed. The pipelined divider can greatly reduce the size of a lookup table with a low cost to overcome the problems involved in the conventional pipelined divider requiring a large lookup table due to its iterative operation type. The pipelined divider has a delay time of 3 cycles in a single precision, and can reduce a chip size by about 1/3 in comparison to the existing pipelined divider.

Abstract translation: 公开了一种带有小查找表的流水线分隔器。 流水线分隔器可以以低成本大大减小查找表的大小，以克服由于其迭代操作类型而需要大型查找表的传统流水线分隔器中涉及的问题。 流水线式分频器的延迟时间为3个周期，单一精度，与现有流水线分频器相比，可将芯片尺寸缩小约1/3。

公开(公告)号：KR1020040011918A

公开(公告)日：2004-02-11

申请号：KR1020020045234

申请日：2002-07-31

Applicant: 학교법인연세대학교

Inventor： 이길환 ,  박우찬 ,  김일산 ,  한탁돈 ,  김신덕

IPC: G06T17/00

Abstract: PURPOSE: An operation method of a pixel cache structure in a three-dimensional graphic accelerator is provided to reduce cache pollution by loading only data with the high probability of being reused, thereby increasing a cache success rate. CONSTITUTION: Information of the existing fragment having the same texture coordinates as a newly inputted segment are detected from a pixel cache(421) and an NT(Non-Temporal) buffer(422). A depth value of the newly inputted fragment is compared with a depth value of the existing fragment. If the depth value of the newly inputted fragment is larger than the depth value of the existing fragment, information of the newly inputted fragment is stored in the NT buffer. If the depth value of the newly inputted fragment is smaller than the depth value of the existing fragment, the information of the newly inputted fragment is stored in the pixel cache. A color reading unit(413) executes a read operation of a color value of the newly inputted fragment. An alpha mixing unit(415) executes alpha mixing to the read color value and a color value mixed in a texture mixing unit(403). A color write unit(417) stores the alpha-mixed color value in the pixel cache.

Abstract translation: 目的：提供三维图形加速器中的像素高速缓存结构的操作方法，通过仅以高重用概率加载数据来减少高速缓存污染，从而提高缓存成功率。 构成：从像素高速缓存（421）和NT（非时间）缓冲器（422）检测具有与新输入的段相同的纹理坐标的现有片段的信息。 将新输入的片段的深度值与现有片段的深度值进行比较。 如果新输入的片段的深度值大于现有片段的深度值，则新输入的片段的信息被存储在NT缓冲器中。 如果新输入片段的深度值小于现有片段的深度值，则新输入片段的信息被存储在像素高速缓存中。 彩色读取单元（413）执行新输入的片段的颜色值的读取操作。 α混合单元（415）对所读取的颜色值和混合在纹理混合单元（403）中的颜色值执行α混合。 彩色写入单元（417）将alpha混合色值存储在像素高速缓存中。

公开(公告)号：KR1020020063058A

公开(公告)日：2002-08-01

申请号：KR1020010003782

申请日：2001-01-26

Applicant: 학교법인연세대학교

Inventor： 박우찬 ,  한탁돈 ,  정철호

IPC: G06F7/42

CPC classification number: G06F7/485 ,  G06F7/49957 ,  G06F2207/3884

Abstract: PURPOSE: A floating point ALU(Arithmetic Logic Unit) is provided to simultaneously perform an IEEE rounding and addition operation on a floating point addition operator by using an SRM(Simultaneous Rounding Method). CONSTITUTION: The unit comprises the first and the second bit-exclusive-logical addition operator(270, 270'), a leading zero controller(300), a multiplexor(310), an alignment right rotator(250), a bit-half adder(160), a CSA(Carry Select Adder), a multiplexor(200) and a compensator(290). The first and the second bit-exclusive-logical addition operator(270, 270') bypass or invert output values of two bit streams of an exponent alignment unit according to the first and the second control signal externally input. The leading zero controller(300) calculates leading zeros by using the signal output from the first bit-exclusive-logical addition operator(270). The multiplexor(310) selects and outputs one between the output value of the leading zero controller(300) and the shift amount for an exponent alignment, according to the third control signal externally input. The alignment right rotator(250) performs an exponent alignment and a normalization on the value output from the multiplexor(300) via a right or a left rotation, and generates a guard bit, a round bit or a sticky bit. The bit-half adder(160) receives the two bit streams output by the alignment right rotator(250) and the second bit-exclusive-logical addition operator(270'), and adds a carry with an addition. The CSA outputs the addition value of the bit-half adder(160) and increases the addition value by one. The multiplexor(200) selects one between the two values output by the CSA according to the fourth control signal. The compensator(290) compensates an LSB(Least Significant Bit) of a value output by the third bit-exclusive-logical addition operator(280').

Abstract translation: 目的：提供浮点ALU（算术逻辑单元），以通过使用SRM（同时舍入方法）来同时对浮点加法运算符执行IEEE舍入加法运算。 构成：该单元包括第一和第二位排他逻辑加法运算符（270,270'），前导零控制器（300），多路复用器（310），对准右旋转器（250），位半部 加法器（160），CSA（进位选择加法器），多路复用器（200）和补偿器（290）。 根据外部输入的第一和第二控制信号，第一和第二位排他逻辑加法运算器（270,270'）旁路或反转指数对准单元的两个比特流的输出值。 前导零控制器（300）通过使用从第一位排除逻辑加法运算器（270）输出的信号来计算前导零。 根据外部输入的第三控制信号，多路复用器（310）在前导零控制器（300）的输出值和指数对准的移位量之间选择并输出一个。 对准右旋转器（250）通过右旋转或左旋转对从多路复用器（300）输出的值进行指数对准和归一化，并产生保护位，圆位或粘点。 位加法器（160）接收由对准右旋转器（250）和第二位排除逻辑加法运算器（270'）输出的两个比特流，并加上进位加法。 CSA输出位半加法器（160）的相加值，并将加法值增加1。 多路复用器（200）根据第四控制信号选择CSA输出的两个值之间的一个。 补偿器（290）补偿由第三位异或逻辑加法运算符（280'）输出的值的LSB（最低有效位）。

公开(公告)号：KR1020020017602A

公开(公告)日：2002-03-07

申请号：KR1020000051066

申请日：2000-08-31

Applicant: 학교법인연세대학교

Inventor： 한탁돈 ,  양성봉 ,  이신준 ,  박우찬

IPC: G06T9/00

Abstract: PURPOSE: A spiral type phase compression method for the 3 dimensional graphic data is provided to execute a compression by converting a triangle mesh into a triangle strip of spiral type in order to dissolve the bottleneck of a memory bus bandwidth while transferring data to a 2 dimensional graphic pipeline. CONSTITUTION: The method comprises steps of selecting a start or restart triangle at random and initializing a search, searching a near triangle being not added to a strip, examining a vertex of the searched triangle, increasing the degree and moving the base vertex pointer, adding a present chain pointer and triangle to the strip, searching the triangle near the base vertex, adding the searched triangle to a triangle strip, moving the base vertex and searching the remaining triangle if a triangle not added to the triangle strip exists.

Abstract translation: 目的：提供一种用于三维图形数据的螺旋型相位压缩方法，用于通过将三角形网格转换为螺旋形三角形条来执行压缩，以便在将数据传输到二维的同时解决存储器总线带宽的瓶颈 图形管道。 构成：该方法包括以下步骤：随机选择起始或重启三角形并初始化搜索，搜索未添加到条带的近三角形，检查所搜索的三角形的顶点，增加度数并移动基本顶点指针，添加 现在的链指针和三角形到条带，搜索基本顶点附近的三角形，将搜索到的三角形添加到三角形条带，移动基本顶点并搜索剩余的三角形，如果没有添加到三角形条带的三角形。

公开(公告)号：KR100487461B1

公开(公告)日：2005-05-03

申请号：KR1020020045236

申请日：2002-07-31

Applicant: 학교법인연세대학교

Inventor： 최문희 ,  박우찬 ,  김신덕 ,  한탁돈

IPC: G06T17/00

Abstract: 본 발명은 완전 하드웨어로 구현한 타일링 트래버설 방식의 주사 변환 유닛 및 방법을 제공하기 위한 것으로서, 스탬프의 원점, 위(RT), 아래(RB), 오른쪽(LB) 위치에 따른 네 개의 탐색 점의 부호를 검출하고, 상기 스탬프와 삼각형의 세 변에 대해 각각 반-평면 변 함수 연산을 수행하는 단계와, 상기 스탬프 네 개의 탐색 점의 결정된 부호를 두 개씩 조합하여 논리합 연산을 수행하고, 상기 논리합 연산한 결과를 논리곱 연산하여 결과 값이 0이면 스탬프가 이동 불가능한 방향인 것으로, 결과 값이 1이면 스탬프가 이동 가능한 방향인 것으로 정의하는 단계와, 상기 정의된 스탬프의 이동 가능한 모든 방향을 토대로 다음에 이동할 위치를 저장하는 저장 콘텍스트, 상기 저장 콘텍스트를 제어하는 최종 플래그, 그리고 타일 경계에 도달 유무 등을 조사하여 최 종 방향을 선택하는 단계와, 다음으로 지정된 스탬프를 입력으로 상기 단계를 반복 수행하는 단계를 포함하여 이루어지는데 있다.

公开(公告)号：KR100441082B1

公开(公告)日：2004-07-21

申请号：KR1020020045237

申请日：2002-07-31

Applicant: 학교법인연세대학교

Inventor： 김정우 ,  이원종 ,  박우찬 ,  김형래 ,  한탁돈 ,  양성봉

IPC: G06T17/10

Abstract: PURPOSE: A three-dimensional texture based volume graphic structure using a visibility-ordered division rendering algorithm and a method therefor are provided to prevent lowering of performance and reduce the size of a required bandwidth. CONSTITUTION: A volume divider(20) decides the size of division volume regions and an order for processing through view point plane of one volume data, and the size and position information of volume information, and generates a three-dimensional texture map. A section generator(40) generates sections of the divided regions by receiving position information of the divided regions and the number of sections per divided region. A geometry operation unit(50) geometrically operates the sections. A three-dimensional texture mapping(60) generates the sections into preliminarily generated three-dimensional texture through the volume information of the corresponding region. An alpha blender(70) alpha-blends the sections one by one. A pixel cache(80) reads the corresponding section information from a frame memory(100) storing the blended section information by the section units to store the read section information, and is used as a cache between the alpha blender and the frame memory.

Abstract translation: 目的：提供一种基于三维纹理的体积图形结构，其使用可见性 - 有序分割呈现算法及其方法，以防止性能降低和减小所需带宽的大小。 组成：体积分割器（20）决定划分体积区域的大小和通过一个体数据的视点平面进行处理的顺序以及体积信息的大小和位置信息，并产生三维纹理图。 区段生成器（40）通过接收分割区域的位置信息和每个分割区域的区段数量来生成分割区域的区段。 几何操作单元（50）几何地操作这些部分。 三维纹理映射（60）通过相应区域的体积信息将区域生成为预先生成的三维纹理。 一台阿尔法搅拌器（70）逐个将各部分混合。 像素高速缓冲存储器（80）从由区段单元存储混合区段信息的帧存储器（100）读取对应的区段信息以存储所读取的区段信息，并用作阿尔法混合器与帧存储器之间的高速缓存。

公开(公告)号：KR100441081B1

公开(公告)日：2004-07-21

申请号：KR1020020045235

申请日：2002-07-31

Applicant: 학교법인연세대학교

Inventor： 이승기 ,  박우찬 ,  한탁돈 ,  이문기

IPC: G06T17/00 ,  G06T1/00

Abstract: PURPOSE: A method for calculating a trigonometric function using a linear equation is provided to reduce an error range through a linear equation, thereby promptly generating video of better quality. CONSTITUTION: A section of an X-axis in a trigonometric function curved surface is equally divided. Values of crossing points where vertical straight lines at boundary points of the divided sections cross the trigonometric function curved surface are obtained. Values of a trigonometric function to values of the sections are obtained by using a straight line equation connecting neighboring points in the obtained crossing points. Color values of fragments are decided by the obtained values of the trigonometric function. The section of the X-axis in a trigonometric function curved surface ranges from 0 to 90 deg.

Abstract translation: 目的：提供一种使用线性方程来计算三角函数的方法，以通过线性方程来减小误差范围，由此迅速生成更好质量的视频。 构成：三角函数曲面中的X轴的一部分被等分。 获得分割部分的边界点处的垂直直线与三角函数曲面交叉的交点的值。 通过使用连接所获得的交叉点中的相邻点的直线方程来获得三角函数对各部分的值的值。 碎片的颜色值由获得的三角函数值决定。 三角函数曲面中X轴的截面范围为0到90度。

公开(公告)号：KR100420860B1

公开(公告)日：2004-03-02

申请号：KR1020010048606

申请日：2001-08-13

Applicant: 학교법인연세대학교

Inventor： 이현석 ,  이택섭 ,  박우찬 ,  양성봉 ,  한탁돈

IPC: G06T17/00

Abstract: PURPOSE: A method of compressing a phase of three-dimensional graphic data using weighted vector sum is provided to compress three-dimensional graphic data in consideration of variations in previous data items to improve compression efficiency. CONSTITUTION: A start triangle is arbitrarily selected. Triangle data to be compressed is inputted(S50). Initial three points are set using one of vertexes of a triangle that was not processed is used as a start point, and the nth vertex is inputted(S52). The sum of vectors is estimated(S54). A difference between a weighted vector sum and actual vertexes is delta-encoded. A difference between an estimated value and an actual value is calculated and stored(S55). Huffman table is constructed on the basis of the delta-encoded value(S56). Huffman tag and encoding data are output. Huffman encoding is performed using the Huffman table and the encoding result is output(S57,S58).

Abstract translation: 目的：提供一种使用加权矢量和来压缩三维图形数据的相位的方法，以考虑到先前数据项的变化来压缩三维图形数据以提高压缩效率。 组成：起始三角形是任意选择的。 输入要压缩的三角形数据（S50）。 使用未经处理的三角形的顶点之一设定初始三点作为起点，输入第N顶点（S52）。 矢量的总和被估计（S54）。 增量矢量和与实际顶点之间的差异是增量编码。 计算并存储估计值和实际值之间的差值（S55）。 霍夫曼表是基于增量编码值构建的（S56）。 输出霍夫曼标签和编码数据。 使用霍夫曼表执行霍夫曼编码，并输出编码结果（S57，S58）。

公开(公告)号：KR1020040011916A

公开(公告)日：2004-02-11

申请号：KR1020020045232

申请日：2002-07-31

Applicant: 학교법인연세대학교

Inventor： 정웅 ,  정종철 ,  박우찬 ,  이문기 ,  한탁돈

IPC: G06F7/52

CPC classification number: G06F7/535 ,  G06F2207/5354

Abstract: PURPOSE: A pipelined ALU(Arithmetic and Logical Unit) having a lookup table of a small size and an operation method thereof are provided to decrease the size of the lookup table while increasing a delay time by one cycle. CONSTITUTION: A dividend X and a divisor Y have a regulated fixed point. The lookup table(LUT2) stores internal parameters and calculates the 1/(Yh)¬2 by using the divisor. The first multiplier(MUL3) calculates the divisor A by multiplying the 1/(Yh)¬2 of the lookup table to the (Yh-Y1) obtained from the dividend X and the divisor Y. The second and the third multiplier(MUL4,MUL5) calculate and output the AX and the AY by respectively operating the divisor A to the dividend Y and the divisor Y. The fourth multiplier(MUL6) outputs a quotient Q by operating the AX to the bit-inverted 2-AY.

Abstract translation: 目的：提供具有小尺寸查找表及其操作方法的流水线ALU（算术和逻辑单元），以减小查找表的大小，同时将延迟时间增加一个周期。 构成：股息X和除数Y具有规定的固定点。 查找表（LUT2）存储内部参数，并使用除数计算1 /（Yh）¬2。 第一乘法器（MUL3）通过将查找表的1 /（Yh）¬2与从被除数X和除数Y获得的（Yh-Y1）相乘来计算除数A.第二和第三乘法器（MUL4， MUL5）通过将除数A分配到除数Y和除数Y来计算和输出AX和AY。第四乘法器（MUL6）通过将AX操作到位反转的2-AY来输出商Q。