公开(公告)号：KR100465371B1

公开(公告)日：2005-01-13

申请号：KR1020010003782

申请日：2001-01-26

Applicant: 학교법인연세대학교

Inventor： 박우찬 ,  한탁돈 ,  정철호

IPC: G06F7/42

CPC classification number: G06F7/485 ,  G06F7/49957 ,  G06F2207/3884

Abstract: A floating-point ALU that performs an IEEE rounding and an addition in parallel in a simultaneous rounding method (SRM) type floating-point adder. The floating-point ALU includes an alignment/normalization section for bypassing or inverting a first fraction part and a second fraction part, performing an alignment by performing a right shift as much as a value obtained from an exponent part or performing a normalization through a left shift by calculating a leading zero with respect to the first fraction part, and obtaining a guard bit (G), round bit (R), and sticky bit (Sy); and an addition and rounding operation section for performing a addition and rounding with respect to the first fraction part and second fraction part outputted through the alignment/normalization section. According to the floating-point ALU, the processing time and the hardware size can be reduced, and the hardware of the SRM can be used as it is.

Abstract translation: 在同时舍入方法（SRM）型浮点加法器中执行IEEE舍入和并行加法的浮点ALU。 浮点ALU包括用于绕过或反转第一分数部分和第二分数部分的对准/归一化部分，通过执行与从指数部分获得的值一样多的右移或者通过执行左归一化来执行对准 通过计算相对于第一小数部分的前导零，并且获得保护位（G），轮位（R）和粘性位（Sy）来移位; 以及相加和舍入运算部分，用于对通过对齐/归一化部分输出的第一分数部分和第二分数部分进行相加和舍入。 根据浮点ALU，可以减少处理时间和硬件大小，并且可以照原样使用SRM的硬件。

公开(公告)号：KR1020020063058A

公开(公告)日：2002-08-01

申请号：KR1020010003782

申请日：2001-01-26

Applicant: 학교법인연세대학교

Inventor： 박우찬 ,  한탁돈 ,  정철호

IPC: G06F7/42

CPC classification number: G06F7/485 ,  G06F7/49957 ,  G06F2207/3884

Abstract: PURPOSE: A floating point ALU(Arithmetic Logic Unit) is provided to simultaneously perform an IEEE rounding and addition operation on a floating point addition operator by using an SRM(Simultaneous Rounding Method). CONSTITUTION: The unit comprises the first and the second bit-exclusive-logical addition operator(270, 270'), a leading zero controller(300), a multiplexor(310), an alignment right rotator(250), a bit-half adder(160), a CSA(Carry Select Adder), a multiplexor(200) and a compensator(290). The first and the second bit-exclusive-logical addition operator(270, 270') bypass or invert output values of two bit streams of an exponent alignment unit according to the first and the second control signal externally input. The leading zero controller(300) calculates leading zeros by using the signal output from the first bit-exclusive-logical addition operator(270). The multiplexor(310) selects and outputs one between the output value of the leading zero controller(300) and the shift amount for an exponent alignment, according to the third control signal externally input. The alignment right rotator(250) performs an exponent alignment and a normalization on the value output from the multiplexor(300) via a right or a left rotation, and generates a guard bit, a round bit or a sticky bit. The bit-half adder(160) receives the two bit streams output by the alignment right rotator(250) and the second bit-exclusive-logical addition operator(270'), and adds a carry with an addition. The CSA outputs the addition value of the bit-half adder(160) and increases the addition value by one. The multiplexor(200) selects one between the two values output by the CSA according to the fourth control signal. The compensator(290) compensates an LSB(Least Significant Bit) of a value output by the third bit-exclusive-logical addition operator(280').

Abstract translation: 目的：提供浮点ALU（算术逻辑单元），以通过使用SRM（同时舍入方法）来同时对浮点加法运算符执行IEEE舍入加法运算。 构成：该单元包括第一和第二位排他逻辑加法运算符（270,270'），前导零控制器（300），多路复用器（310），对准右旋转器（250），位半部 加法器（160），CSA（进位选择加法器），多路复用器（200）和补偿器（290）。 根据外部输入的第一和第二控制信号，第一和第二位排他逻辑加法运算器（270,270'）旁路或反转指数对准单元的两个比特流的输出值。 前导零控制器（300）通过使用从第一位排除逻辑加法运算器（270）输出的信号来计算前导零。 根据外部输入的第三控制信号，多路复用器（310）在前导零控制器（300）的输出值和指数对准的移位量之间选择并输出一个。 对准右旋转器（250）通过右旋转或左旋转对从多路复用器（300）输出的值进行指数对准和归一化，并产生保护位，圆位或粘点。 位加法器（160）接收由对准右旋转器（250）和第二位排除逻辑加法运算器（270'）输出的两个比特流，并加上进位加法。 CSA输出位半加法器（160）的相加值，并将加法值增加1。 多路复用器（200）根据第四控制信号选择CSA输出的两个值之间的一个。 补偿器（290）补偿由第三位异或逻辑加法运算符（280'）输出的值的LSB（最低有效位）。