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1.
公开(公告)号:KR1020150112312A
公开(公告)日:2015-10-07
申请号:KR1020140036208
申请日:2014-03-27
Applicant: 한국과학기술원
Abstract: 낮은비용으로고품질의마이크로프리즘미러를제조할수 있는방법및 이와같이제조된마이크로프리즘미러와미세유체장치가개시된다. 마이크로프리즘미러의제조방법은, 실리콘질화막이형성된실리콘웨이퍼를에칭하여직각이등변삼각형형상의 V자형트렌치가형성된 Si 마스터몰드를형성하는단계, 상기마스터몰드를복제하여 PDMS(polydimethyl siloxane) 금형을형성하는단계, 상기 PDMS 금형을 PDMS 플레이트상에배치하여미세유체채널을형성하는단계, 상기미세유체채널에 UV 경화성고분자(UV curable polymer)를충진시켜서경화시켜서마이크로프리즘을형성하는단계및 상기마이크로프리즘의빗변에반사물질을코팅하여반사코팅막을형성하는단계를포함한다.
Abstract translation: 公开了一种以低成本制造高质量微棱镜的方法,由其制造的微棱镜和微流体装置。 微棱镜的制造方法可以包括以下步骤:通过蚀刻具有氮化硅膜的硅晶片来形成具有V形沟槽的Si母模; 通过复制母模形成聚二甲基硅氧烷(PDMS)模具; 通过将PDMS模具布置在PDMS板上形成微流体通道; 通过在微流体通道中填充和固化UV可固化聚合物形成微棱镜; 以及通过用反射材料涂覆微棱镜的斜边来形成反射涂膜。
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2.
公开(公告)号:KR101563190B1
公开(公告)日:2015-10-27
申请号:KR1020140036208
申请日:2014-03-27
Applicant: 한국과학기술원
Abstract: 낮은비용으로고품질의마이크로프리즘미러를제조할수 있는방법및 이와같이제조된마이크로프리즘미러와미세유체장치가개시된다. 마이크로프리즘미러의제조방법은, 실리콘질화막이형성된실리콘웨이퍼를에칭하여직각이등변삼각형형상의 V자형트렌치가형성된 Si 마스터몰드를형성하는단계, 상기마스터몰드를복제하여 PDMS(polydimethyl siloxane) 금형을형성하는단계, 상기 PDMS 금형을 PDMS 플레이트상에배치하여미세유체채널을형성하는단계, 상기미세유체채널에 UV 경화성고분자(UV curable polymer)를충진시켜서경화시켜서마이크로프리즘을형성하는단계및 상기마이크로프리즘의빗변에반사물질을코팅하여반사코팅막을형성하는단계를포함한다.
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公开(公告)号:KR1020080015666A
公开(公告)日:2008-02-20
申请号:KR1020060077295
申请日:2006-08-16
IPC: G02F1/136
CPC classification number: H01L21/02672 , H01L21/02532 , H01L27/1277 , H01L27/1281
Abstract: A method for manufacturing a thin film transistor substrate is provided to crystallize an amorphous silicon film with a minimum ion amount required for crystallizing to minimize the amount of nickel contained in the crystallized silicon layer by using a sacrificial layer, thereby improving the quality of the thin film transistor substrate. An amorphous silicon film is formed on an insulating substrate(110). A sacrificial film having an embossed surface is formed on the amorphous silicon film. The amorphous silicon film is crystallized into a polycrystalline silicon layer by contacting a metal plate with the sacrificial film and performing thermal treatment on the amorphous silicon film. The metal plate and the sacrificial film are removed. The polycrystalline silicon film is pattern-etched to form a semiconductor pattern(151). A gate insulating layer(140) is formed to cover the semiconductor pattern. A gate line is formed on the gate insulating layer, wherein a portion of the gate line overlaps the semiconductor pattern. Source and drain regions(153,155) are formed by heavily doping conductive impurities into portions of the semiconductor pattern. An interlayer insulating layer is formed to cover the gate line and the semiconductor pattern. A data line(171) and an output electrode(175) respectively connected to the source and drain regions are formed on the interlayer insulating layer.
Abstract translation: 提供一种制造薄膜晶体管基板的方法,以结晶所需的最小离子量使非晶硅膜结晶,以通过使用牺牲层将结晶硅层中所含的镍的量最小化,从而提高薄膜晶体管的质量 薄膜晶体管衬底。 在绝缘基板(110)上形成非晶硅膜。 在非晶硅膜上形成具有压花表面的牺牲膜。 通过使金属板与牺牲膜接触并对非晶硅膜进行热处理,将非晶硅膜结晶成多晶硅层。 去除金属板和牺牲膜。 对多晶硅膜进行图案蚀刻以形成半导体图案(151)。 形成栅极绝缘层(140)以覆盖半导体图案。 栅极线形成在栅极绝缘层上,其中栅极线的一部分与半导体图案重叠。 源极和漏极区(153,155)通过将导电杂质重掺杂到半导体图案的部分中而形成。 形成层间绝缘层以覆盖栅极线和半导体图案。 分别连接到源区和漏区的数据线(171)和输出电极(175)形成在层间绝缘层上。
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