公开(公告)号：KR100368133B1

公开(公告)日：2003-01-15

申请号：KR1020000015697

申请日：2000-03-28

Applicant: 한국과학기술원

Inventor： 국정훈 ,  유회준

IPC: G11C7/00

CPC classification number: G11C11/4091 ,  G11C7/06 ,  G11C2207/005

Abstract: A method of storing information in a memory cell. The method writes information via only the bit-line that is connected to a memory cell with respect to a word-line, and thus reduces the overall power consumption in the memory by reducing the unnecessary power consumption occurring from the change of voltage level in the bit-line that is not connected to a memory cell. To this end, a method of storing information in a memory cell having a sense amplifier which differentially amplifies a difference in voltage level between a pair of bit-lines is provided, the method comprising the steps of activating a word-line connected to the memory cell to be accessed, differentially amplifying the difference in voltage level between the pair of bit-lines coupled to the memory cell to be accessed, and selecting only one bit-line that is connected to the memory cell among the pair of bit-lines and rewriting the information via the one bit-line.

Abstract translation: 一种将信息存储在存储单元中的方法。 该方法仅经由与字线连接的存储单元的位线写入信息，因此通过减少由于存储单元中的电压电平的改变而出现的不必要的功耗，降低了存储器中的整体功耗 未连接到存储单元的位线。 为此，提供了一种将信息存储在具有差分放大一对位线之间的电压电平差的读出放大器的存储单元中的方法，该方法包括以下步骤：激活连接到存储器的字线 将要被访问的存储单元的一对位线之间的电压差的差分放大，在该一对位线中仅选择与存储单元连接的一条位线， 通过一条位线重写信息。

公开(公告)号：KR1020010092954A

公开(公告)日：2001-10-27

申请号：KR1020000015697

申请日：2000-03-28

Applicant: 한국과학기술원

Inventor： 국정훈 ,  유회준

IPC: G11C7/00

CPC classification number: G11C11/4091 ,  G11C7/06 ,  G11C2207/005

Abstract: PURPOSE: A method for storing memory cell information is provided to reduce a power dissipation of a memory by reducing unnecessary power consumption generated because of transition of a bit line not connected with a cell. CONSTITUTION: Bit line selection signals(BISL_0,BISL_1,BISH_0,BISH_1) for a SBR(Single Bitline Rewriting) are applied to switching devices respectively connected between bit lines(BL,/BL) and a sense amplifier(SA) to select a cell array adjacent upward and downward one sense amplifier arranged on four word line pitch. According to the above structure, there is no increase of area. The bit line select signal can control the bit lines respectively.

Abstract translation: 目的：提供一种用于存储存储单元信息的方法，通过减少由于与单元不连接的位线的转变而产生的不必要的功率消耗来减少存储器的功耗。 构成：用于SBR（单位线重写）的位线选择信号（BISL_0，BISL_1，BISH_0，BISH_1）被应用于分别连接在位线（BL，/ BL）和读出放大器（SA）之间的开关器件，以选择一个单元 阵列相邻的上下一个读出放大器布置在四个字线间距上。 根据上述结构，没有增加面积。 位线选择信号可以分别控制位线。

公开(公告)号：KR1020030020141A

公开(公告)日：2003-03-08

申请号：KR1020010053827

申请日：2001-09-03

Applicant: 한국과학기술원

Inventor： 우람찬 ,  윤치원 ,  국정훈 ,  이세중 ,  유회준

IPC: G06F3/14

Abstract: PURPOSE: A three dimensional computer graphics operation system is provided to install a bandwidth equalizer between a main operation processor and three dimensional computer graphics accelerators having different bandwidths for a high efficient data transmission so that it can implement a real time three dimensional computer graphics at a portable terminal. CONSTITUTION: The system comprises three dimensional computer graphics accelerators(300), a moving picture regeneration accelerator(410), and a bandwidth equalizer (200). The moving picture regeneration accelerator(410), connected to a main operation processor(100) via the bandwidth equalizer(200), accelerates a display of the three dimensional computer graphics. The three dimensional computer graphics accelerators(300) are workstation level hardwares for accelerating three dimensional graphic display with a high speed. The bandwidth equalizer(200) is a bus structure for connecting the three dimensional computer graphic accelerator(300) and the moving picture regeneration accelerator(410) to the main operation processor(100). The bandwidth equalizer(200) synchronizes the bandwidth of the three dimensional computer graphics accelerator(300) to that of the main operation processor(100) for enabling a data transmission between them. Also, the bandwidth equalizer(200) synchronizes the bandwidth of the moving picture regeneration accelerator(410) with that of the main operation processor(100).

Abstract translation: 目的：提供一种三维计算机图形操作系统，用于在具有不同带宽的主操作处理器和三维计算机图形加速器之间安装带宽均衡器，用于高效数据传输，从而可以实现三维计算机图形处理 便携式终端。 构成：该系统包括三维计算机图形加速器（300），运动图像再生加速器（410）和带宽均衡器（200）。 经由带宽均衡器（200）连接到主操作处理器（100）的运动画面再生加速器（410）加速三维计算机图形的显示。 三维计算机图形加速器（300）是用于加速高速三维图形显示的工作站级硬件。 带宽均衡器（200）是用于将三维计算机图形加速器（300）和运动图像再生加速器（410）连接到主操作处理器（100）的总线结构。 带宽均衡器（200）使三维计算机图形加速器（300）的带宽与主操作处理器（100）的带宽同步，以实现它们之间的数据传输。 此外，带宽均衡器（200）使运动图像再生加速器（410）的带宽与主运算处理器（100）的带宽同步。