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Patent Agency Ranking
公开(公告)号：KR101402945B1
公开(公告)日：2014-06-05
申请号：KR1020120047682
申请日：2012-05-04
Applicant: 한국과학기술원
IPC: H03B5/12
Abstract: 시링킹팩터(shrinking factor)를 보다 더 작게 만들 수 있고 1-최하위 비트(LSB)에 따라 변하는 유닛 캐패시턴스(unit capacitance)를 더 줄어들게 하는 것이 가능하도록, 인덕터와 캐패시터로 구성되는 엘씨탱크(LC-tank)와, 엘씨탱크에 병렬로 연결되는 제1트랜지스터 및 제2트랜지스터와, 제1트랜지스터와 캐스코드(cascode) 방식으로 연결되는 제3트랜지스터와, 제2트랜지스터와 캐스코드 방식으로 연결되는 제4트랜지스터와, 제3트랜지스터와 제4트랜지스터의 소스에 연결되는 유닛 캐패시터와, 하나는 제3트랜지스터의 드레인과 소스에 연결되고 다른 하나는 제4트랜지스터의 드레인과 소스에 연결되는 한쌍의 보조캐패시터를 포함하는 양자화 잡음을 감소시킨 고해상도 디지털 제어 발진기를 제공한다.
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公开(公告)号：KR1020130124064A
公开(公告)日：2013-11-13
申请号：KR1020120047682
申请日：2012-05-04
Applicant: 한국과학기술원
IPC: H03B5/12
CPC classification number: H03B5/124 , H03B5/1212 , H03B5/1228 , H03B5/24 , H03B2200/0088
Abstract: Provided is a high-resolution DCO structure for reducing quantization noise which is capable of making shrinking factors smaller and reducing unit capacitance varying according to 1-least significant bits (LSBs), comprising: an LC-tank comprising an inductor and a capacitor; a first transistor and a second transistor connected to the LC-tank in parallel; a third transistor connected to the first transistor in a cascade mode; a fourth transistor connected to the second transistor in the cascade mode; a unit capacitor connected to sources of the third transistor and the fourth transistor, respectively; a pair of sub capacitors in which one is connected to the drain and source of the third transistor and the other is connected to the drain and source of the fourth transistor.
Abstract translation: 提供了一种用于降低量化噪声的高分辨率DCO结构，其能够使缩小因子更小并且减小单位电容根据1-最低有效位（LSB）而变化，包括：包括电感器和电容器的LC槽; 并联连接到LC箱的第一晶体管和第二晶体管; 以级联模式连接到第一晶体管的第三晶体管; 以级联模式连接到第二晶体管的第四晶体管; 分别连接到第三晶体管和第四晶体管的源极的单位电容器; 一对副电容器，其中一个连接到第三晶体管的漏极和源极，另一个连接到第四晶体管的漏极和源极。
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公开(公告)号：KR1020120055769A
公开(公告)日：2012-06-01
申请号：KR1020100116804
申请日：2010-11-23
IPC: H03K3/0231 , H03F3/45
CPC classification number: H03K3/0322 , H03F3/45475 , H03K5/1252 , H03K5/133 , H03K2005/00208
Abstract: PURPOSE: A voltage controlled oscillator and a method for eliminating phase noise are provided to eliminate phase noise by blocking currents flowing into a variable frequency transistor in a voltage level conversion section. CONSTITUTION: A voltage controlled oscillator(10) comprises a first delay cell(110), a second delay cell(120), a third delay cell(130), and a fourth delay cell(140) consisting of a plurality of stages. The voltage controlled oscillator is composed of four stages. A first stage includes the first delay cell. A second stage includes the second delay cell. A third stage includes the third delay cell. A fourth stage includes the fourth delay cell. The first delay cell to the fourth delay cell can be formed into a ring shape.
Abstract translation: 目的：提供压控振荡器和消除相位噪声的方法，以通过阻断流入电压电平转换部分中的可变频率晶体管的电流来消除相位噪声。 构成：压控振荡器（10）包括第一延迟单元（110），第二延迟单元（120），第三延迟单元（130）和由多个级组成的第四延迟单元（140）。 压控振荡器由四个阶段组成。 第一级包括第一延迟单元。 第二级包括第二延迟单元。 第三级包括第三延迟单元。 第四级包括第四延迟单元。 到第四延迟单元的第一延迟单元可以形成为环形。
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公开(公告)号：KR101910886B1
公开(公告)日：2018-10-24
申请号：KR1020130010225
申请日：2013-01-30
IPC: H03B5/12
Abstract: 실시예들에따른차동전압제어발진기는 LC 공진부, 피드백트랜지스터부및 커패시터디바이더부를포함한다. 차동전압제어발진기의출력신호는피드백트랜지스터의게이트노드에서스윙하고, 커패시터디바이더회로와의조합으로인하여그라운드전위보다낮은전압까지스윙할수 있다.
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公开(公告)号：KR1020140098876A
公开(公告)日：2014-08-11
申请号：KR1020130010225
申请日：2013-01-30
IPC: H03B5/12
CPC classification number: H03B5/1209 , H03B5/1228 , H03B5/1243 , H03B2201/0208
Abstract: A differential voltage controlled oscillator according to embodiments of the present invention includes an LC resonance unit, a feedback transistor unit, and a capacitor divider unit. The output signal of the differential voltage controlled oscillator is swung at a gate node of the feedback transistor and is swung up to a voltage lower than a ground potential by combination with a capacitor divider circuit.
Abstract translation: 根据本发明的实施例的差分压控振荡器包括LC谐振单元，反馈晶体管单元和电容分配器单元。 差分压控振荡器的输出信号在反馈晶体管的栅极节点摆动，并通过与电容分压器电路的组合而摆动到低于地电位的电压。
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