公开(公告)号：KR101209458B1

公开(公告)日：2012-12-07

申请号：KR1020100134135

申请日：2010-12-24

Applicant: 한국과학기술원

Inventor： 김정호 ,  김주희 ,  박준서

IPC: H01L23/48 ,  H01L23/12

CPC classification number: H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225

Abstract: 관통실리콘비아의신호특성을개선하기위한반도체칩이개시된다. 반도체칩은기판, 관통실리콘비아(through silicon via) 및저항구조물을포함한다. 관통실리콘비아는기판의일면과다른일면을관통하여형성된다. 저항구조물은기판과관통실리콘비아사이에도전성패턴들을통하여전기적으로연결된다. 따라서, 반도체칩을통하여전송되는입출력신호의전압여유및 타이밍여유가개선될수 있다.

公开(公告)号：KR1020110042393A

公开(公告)日：2011-04-27

申请号：KR1020090099036

申请日：2009-10-19

Applicant: 에스케이하이닉스 주식회사 ,  한국과학기술원

Inventor： 이준호 ,  김현석 ,  정부호 ,  조선기 ,  김양희 ,  김영원 ,  김정호 ,  김주희

IPC: H01L23/12 ,  H01L23/52

CPC classification number: H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2924/00012

Abstract: PURPOSE: A semiconductor device having the silicon penetrating via structure is provided to alleviate the capacitive effect of TSV structure by using the ohmic contact. CONSTITUTION: A chip penetrating via(TSV) is inserted into the semiconductor wafer. An insulation layer is arranged around the chip penetration via to separate the semiconductor wafer and the chip penetration via. The ohmic contact layer is arranged in order to surround the chip penetration via on the surface part of the semiconductor wafer. The connection wiring electrically connects the chip penetration via and the ohmic contact layer.

Abstract translation: 目的：提供具有硅穿透结构的半导体器件，以通过使用欧姆接触来减轻TSV结构的电容效应。 构成：穿透通孔（TSV）的芯片插入半导体晶片。 绝缘层布置在芯片穿透通孔周围以分离半导体晶片和芯片穿透通孔。 欧姆接触层被布置为围绕半导体晶片的表面部分上的芯片穿透通孔。 连接布线将芯片穿透通孔和欧姆接触层电连接。

公开(公告)号：KR1020120072407A

公开(公告)日：2012-07-04

申请号：KR1020100134135

申请日：2010-12-24

Applicant: 한국과학기술원

Inventor： 김정호 ,  김주희 ,  박준서

IPC: H01L23/48 ,  H01L23/12

CPC classification number: H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225

Abstract: PURPOSE: A semiconductor chip, a manufacturing method thereof, and a semiconductor module including the same are provided to improve the timing margin and voltage margin of input and output signals by including a resistance structure which is electrically connected between the through silicon via and a substrate. CONSTITUTION: A through silicon via(110) passes through both sides of a substrate(170). A resistance structure(130) is electrically connected between the through silicon via and the substrate. A pad(150) is formed on the substrate with a contact or via shape. A redistribution layer(171) includes a first conductive pattern(120) and a second conductive pattern(140). The first conductive pattern electrically connects the through silicon via and the resistance structure.

Abstract translation: 目的：提供一种半导体芯片及其制造方法以及包括该半导体芯片的半导体模块，以通过包括电连接在通孔硅通孔和基板之间的电阻结构来改善输入和输出信号的时序余量和电压余量 。 构成：穿硅通孔（110）穿过衬底（170）的两侧。 电阻结构（130）电连接在贯通硅通孔和基板之间。 衬底（150）以接触或通孔形状形成在衬底上。 再分配层（171）包括第一导电图案（120）和第二导电图案（140）。 第一导电图形电连接通孔硅通孔和电阻结构。