-
公开(公告)号：KR1020140003824A
公开(公告)日：2014-01-10
申请号：KR1020120070644
申请日：2012-06-29
Applicant: 에스케이하이닉스 주식회사 , 한국과학기술원
IPC: H01L21/768 , H01L21/28
Abstract: The present invention relates to a technique for reducing the propagation of the noise of a harmonic wave component to a substrate due to a signal applied to a TSV. According to the present invention, a semiconductor device includes a TSV penetrating a substrate and receiving a first signal and a bias voltage supply device supplying a bias voltage between the TSV and the substrate to form at least part of a first region defined by a voltage for the substrate of a first signal in a second region. At this time, constant capacitance between the TSV and the substrate is maintained in the second region.
Abstract translation: 本发明涉及一种用于减少由于施加到TSV的信号而将谐波分量的噪声传播到衬底的技术。 根据本发明，半导体器件包括穿透衬底并接收第一信号的TSV和在TSV和衬底之间提供偏置电压的偏置电压供给装置，以形成由电压定义的第一区域的至少一部分， 在第二区域中的第一信号的衬底。 此时，在第二区域中保持TSV和衬底之间的恒定电容。
-
2.发明授权
公开(公告)号：KR101166485B1
公开(公告)日：2012-07-19
申请号：KR1020100133124
申请日：2010-12-23
Applicant: 한국과학기술원
IPC: G01R19/165
Abstract: 전류 측정 소자는 제1 도전성 패턴 및 적어도 하나의 제2 도전성 패턴을 포함한다. 제1 전도성은 패턴 기판의 제1 면에 형성된다. 적어도 하나의 제2 도전성 패턴은 제1 도전성 패턴 주변에 코일(coil) 구조의 도전 경로가 형성되도록 기판의 제2 면에 위치하는 재배선층(redistribution layer)에 형성된다. 따라서, 전류 측정 소자는 제1 도전성 패턴에 흐르는 입력 전류에 응답하여 코일 구조의 도전 경로 상에 형성되는 유도 전압에 기초하여 입력 전류의 세기를 정밀하게 측정할 수 있다.
-
公开(公告)号：KR1020120072407A
公开(公告)日：2012-07-04
申请号：KR1020100134135
申请日：2010-12-24
Applicant: 한국과학기술원
CPC classification number: H01L2224/06181 , H01L2224/13025 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225
Abstract: PURPOSE: A semiconductor chip, a manufacturing method thereof, and a semiconductor module including the same are provided to improve the timing margin and voltage margin of input and output signals by including a resistance structure which is electrically connected between the through silicon via and a substrate. CONSTITUTION: A through silicon via(110) passes through both sides of a substrate(170). A resistance structure(130) is electrically connected between the through silicon via and the substrate. A pad(150) is formed on the substrate with a contact or via shape. A redistribution layer(171) includes a first conductive pattern(120) and a second conductive pattern(140). The first conductive pattern electrically connects the through silicon via and the resistance structure.
Abstract translation: 目的：提供一种半导体芯片及其制造方法以及包括该半导体芯片的半导体模块，以通过包括电连接在通孔硅通孔和基板之间的电阻结构来改善输入和输出信号的时序余量和电压余量 。 构成：穿硅通孔（110）穿过衬底（170）的两侧。 电阻结构（130）电连接在贯通硅通孔和基板之间。 衬底（150）以接触或通孔形状形成在衬底上。 再分配层（171）包括第一导电图案（120）和第二导电图案（140）。 第一导电图形电连接通孔硅通孔和电阻结构。
-
4.发明授权반도체 칩 패키지, 이를 포함하는 반도체 모듈, 전자 시스템 및 반도체 칩 패키지의 제조 방법 有权半导体芯片封装，包括半导体芯片封装的半导体模块，包括半导体模块的电子系统和制造半导体芯片封装的方法
公开(公告)号：KR101104380B1
公开(公告)日：2012-01-16
申请号：KR1020100129677
申请日：2010-12-17
Applicant: 한국과학기술원
CPC classification number: H01L2224/16145
Abstract: PURPOSE: A semiconductor chip package, a semiconductor module including the same, an electronic system, and a manufacturing method of the semiconductor chip package are provided to effectively release a heat which is generated in the core region of a first semiconductor chip by arranging a plurality of second semiconductor chips in the interface region of a first semiconductor chip. CONSTITUTION: A first semiconductor chip comprises an interface region(114) which is equipped with a core region(112) and a plurality of first input-output pads(116). A plurality of second semiconductor chips(120) comprises a first side and a second side which are faced each other. The second semiconductor chip comprises a plurality of second input-output pads(122) which is electrically connected with the first input-output pad. A plurality of second semiconductor chips is arranged in the interface region in order to be directly touched with a plurality of first input-output pads. The first semiconductor chip comprises a fixing means which fixes a plurality of second semiconductor chips.
Abstract translation: 目的：提供一种半导体芯片封装，包括该半导体芯片封装的半导体模块，电子系统和半导体芯片封装的制造方法，以通过布置多个第一半导体芯片来有效地释放在第一半导体芯片的芯区域中产生的热量 的第二半导体芯片在第一半导体芯片的界面区域中。 构成：第一半导体芯片包括配备有芯区域（112）和多个第一输入 - 输出焊盘（116）的界面区域（114）。 多个第二半导体芯片（120）包括彼此面对的第一侧面和第二侧面。 第二半导体芯片包括与第一输入 - 输出焊盘电连接的多个第二输入 - 输出焊盘（122）。 多个第二半导体芯片布置在接口区域中，以便与多个第一输入 - 输出焊盘直接接触。 第一半导体芯片包括固定多个第二半导体芯片的固定装置。
-
公开(公告)号：KR1020090108193A
公开(公告)日：2009-10-15
申请号：KR1020080033490
申请日：2008-04-11
Applicant: 한국과학기술원
CPC classification number: H01L2224/16145 , H01L2224/48091 , H01L2224/73257 , H01L2924/10253 , H01L2924/00014 , H01L2924/00
Abstract: PURPOSE: A stacked chip package including a through wafer via is provided to stably supply a power source by transmitting signals to through wafer via or wire bond after dividing the signals according to frequencies. CONSTITUTION: A stacked chip package(700) includes a semiconductor substrate(780), a plurality of semiconductor chips(710,720,730,740), a plurality of first through wafer vias(713), and a plurality of second through wafer vias(711a,711b,712a,712b). The semiconductor chips are laminated on the semiconductor substrate. The first through wafer vias are formed on a first same coordinate of the semiconductor chips, penetrate the semiconductor chips, and transmit a high frequency signal. The second through wafer vias are formed on a second same coordinate different from the first same coordinate, penetrate the semiconductor chips, and transmit a low frequency signal.
Abstract translation: 目的：提供包括贯通晶片通孔的堆叠式芯片封装，以便根据频率对信号进行分割后，通过传输信号到晶圆通孔或引线键来稳定地供电。 构成：堆叠式芯片封装（700）包括半导体衬底（780），多个半导体芯片（710,720,730,740），多个第一到晶圆通孔（713）和多个第二通孔晶片通孔（711a，711b， 712A，712B）。 半导体芯片层叠在半导体基板上。 第一贯穿晶片通孔形成在半导体芯片的第一相同坐标上，穿透半导体芯片并传输高频信号。 第二贯穿晶片通孔形成在不同于第一相同坐标的第二相同坐标上，穿透半导体芯片，并传输低频信号。
-
Patent Agency Ranking
公开(公告)号：KR101846562B1
公开(公告)日：2018-04-06
申请号：KR1020120088725
申请日：2012-08-14
Applicant: 에스케이하이닉스 주식회사 , 한국과학기술원
CPC classification number: G01R31/2601 , G01R31/2853 , G01R31/31926
Abstract: 본발명은관통전극을포함하는기판과그 상부의금속배선층사이의정상연결여부, 관통전극과기판사이의절연여부등을테스트할수 있는반도체테스트장치, 반도체장치및 반도체테스트방법에관한것이다. 본발명에의한반도체테스트장치는제어단자를포함한발진기및 관통전극또는상기관통전극과연결된금속배선층과상기제어단자를선택적으로연결하는스위치를포함한다.
-
公开(公告)号：KR1020120069797A
公开(公告)日：2012-06-29
申请号：KR1020100131097
申请日：2010-12-21
Applicant: 한국과학기술원
Abstract: PURPOSE: A through silicon via capacitor, a manufacturing method thereof, and a 3D integrated circuit are provided to obtain high capacitance by using the silicon through electrode of a vertical structure. CONSTITUTION: A first substrate(100) includes a plurality of circuit boards(11) and a plurality of TSV(Through Silicon Via) capacitors(15). An intermediate layer(300) is formed between the plurality of circuit boards and includes a solder bump(330) and an underfill resin layer(310). The solder bump electrically connects the plurality of circuit boards. A second substrate(200) includes a plurality of active regions, a wiring region, and a TSV capacitor.
Abstract translation: 目的：提供一种通过硅通孔电容器，其制造方法和3D集成电路，以通过使用垂直结构的硅通孔来获得高电容。 构成：第一基板（100）包括多个电路板（11）和多个TSV（贯通硅通孔）电容器（15）。 在多个电路板之间形成中间层（300），并包括焊料凸块（330）和底部填充树脂层（310）。 焊料凸块电连接多个电路板。 第二基板（200）包括多个有源区，布线区和TSV电容。
-
公开(公告)号：KR101288802B1
公开(公告)日：2013-07-23
申请号：KR1020120006103
申请日：2012-01-19
Applicant: 한국과학기술원
IPC: H01L27/04
Abstract: PURPOSE: An electromagnetic interference (EMI) cancelation circuit, a semiconductor device having the same, and an EMI method are provided to generate an extra noise, thereby offsetting an EMI. CONSTITUTION: An electromagnetic interference (EMI) cancelation circuit includes a noise source (120) and a power distribution network (140). The noise source generates an output signal in response to a voltage signal in order to generate an extra noise (NS2). The extra noise has a phase opposite to the phase of a simultaneous switching noise (NS1). The voltage signal has a phase opposite to the phase of a clock signal. The power distribution network generates the extra noise.
Abstract translation: 目的：提供电磁干扰（EMI）消除电路，具有该电磁干扰（EMI）消除电路，具有该EMI消除电路的半导体器件和EMI方法，以产生额外的噪声，从而抵消EMI。 构成：电磁干扰（EMI）消除电路包括噪声源（120）和配电网络（140）。 噪声源响应于电压信号产生输出信号以产生额外的噪声（NS2）。 额外的噪声具有与同时开关噪声（NS1）的相位相反的相位。 电压信号具有与时钟信号的相位相反的相位。 配电网络产生额外的噪音。
-
公开(公告)号：KR101232645B1
公开(公告)日：2013-02-13
申请号：KR1020100131486
申请日：2010-12-21
Applicant: 한국과학기술원
IPC: H01L23/48 , H01L23/045 , H01L23/055
CPC classification number: H01L24/73 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2924/14 , H01L2924/15311 , H01L2924/30107 , H01L2924/00012 , H01L2924/00
Abstract: 3차원 집적 회로는 복수의 제1 전원 핀들 및 복수의 제2 전원 핀들을 포함한다. 제1 전원 핀들은 적어도 하나의 회로 기판 상에서 제1 방향으로 제1 간격마다 배치되고, 서로 같은 극성을 갖는다. 제2 전원 핀들은 적어도 하나의 회로 기판 상에서 제1 전원 핀들로부터 제1 방향과 직교하는 제2 방향으로 제1 거리만큼 이격되어 제1 방향으로 제2 간격마다 배치되며, 제1 전원 핀들과 반대의 극성을 갖는다. 따라서, 같은 극성을 갖는 전원 핀들이 일렬로 배열되므로 전원 핀들의 인덕턴스가 감소하여 3차원 집적 회로에서 발생하는 전원 노이즈가 저감된다.
-
公开(公告)号：KR1020140022979A
公开(公告)日：2014-02-26
申请号：KR1020120088725
申请日：2012-08-14
Applicant: 에스케이하이닉스 주식회사 , 한국과학기술원
CPC classification number: G01R31/2601 , G01R31/2853 , G01R31/31926
Abstract: The present invention relates to a semiconductor test device, a semiconductor device and a method for testing a semiconductor device, capable of testing normal connection between a substrate including a through electrode and a metal line on the upper part of the same, and insulation between the through electrode and the substrate etc. A semiconductor test device according to the present invention includes a switch for connecting an oscillator including a control port and the through electrode or the control port and a metal line layer connected to the through electrode selectively.
Abstract translation: 半导体测试装置，半导体器件和半导体器件测试方法本发明涉及一种半导体测试器件，半导体器件和半导体器件测试方法，该半导体器件能够测试包括贯通电极的基板和其上部的金属线之间的正常连接， 通过电极和基板等。根据本发明的半导体测试装置包括用于连接包括控制端口和贯通电极或控制端口的振荡器的开关和选择性地连接到通孔的金属线层。
-
-
-
-
-
-
-
-
-
Search Results
15
records
(took 0.025 seconds)
