公开(公告)号：KR1020080014531A

公开(公告)日：2008-02-14

申请号：KR1020060076366

申请日：2006-08-11

Applicant: 삼성전자주식회사 ,  한국과학기술원

Inventor： 최정연 ,  원효식 ,  신영수 ,  김형옥 ,  허세완

IPC: G11C5/14

Abstract: A method for decreasing a leakage current using voltage control and power gating and a semiconductor device using the method are provided to decrease the leakage current and to maintain data stored in a register at the same time, by blocking the leakage current generated in a circuit configuration element not used temporarily. A semiconductor device comprises a digital circuit(110), a power switch(120), a register(130_1,130_2,130_3,...), a current blocking circuit(140) and a power saving device(150). The power switch applies one of an operation voltage and a non-operation voltage to the digital circuit according to the operation of the digital circuit. The register maintains stored data by being connected to the voltage selected by the power switch. The current blocking part blocks a leakage current generated in the digital circuit. The power saving device controls the power switch and the current blocking part by outputting a selection signal.

Abstract translation: 提供一种使用电压控制和功率门控来减少漏电流的方法以及使用该方法的半导体器件，通过阻止在电路配置中产生的漏电流来同时减少泄漏电流并保持同时存储在寄存器中的数据 元素暂时不使用 半导体器件包括数字电路（110），电源开关（120），寄存器（130_1,130_2,130_3，...），电流阻断电路（140）和省电设备（150）。 根据数字电路的动作，电源开关对数字电路施加工作电压和非工作电压之一。 寄存器通过连接到由电源开关选择的电压来保持存储的数据。 电流阻塞部分阻塞在数字电路中产生的漏电流。 省电装置通过输出选择信号来控制电源开关和电流阻断部分。

公开(公告)号：KR100857826B1

公开(公告)日：2008-09-10

申请号：KR1020070037863

申请日：2007-04-18

Applicant: 한국과학기술원

Inventor： 신영수 ,  김형옥

IPC: G11C5/14

CPC classification number: H03K19/0016 ,  H03K17/302 ,  H03K19/0185

Abstract: A power network circuit adopting zigzag power gating and a semiconductor device including the same are provided to be used easily in implementing semi-custom scheme on the basis of a conventional standard cell as having low power consumption. At least one pair of first rails(1000) comprises a power supply voltage line(1200) supplying a power supply voltage and a virtual base voltage line(1300) connected to a base voltage line of another rail pair through a first power gating circuit(1100). At least one pair of second rails(2000) comprises a virtual power supply voltage line(2200) connected to a power supply voltage line of another adjacent rail pair through a second power gating circuit(2100) and a base voltage line(2300) supplying a base voltage. The first power gating circuit is a NMOS(N-channel Metal -Oxide Semiconductor) transistor switching the connection of the base voltage line and the virtual base voltage line of the adjacent rail pair, in response to an inversion signal of a sleep mode control signal.

Abstract translation: 提供采用锯齿形电源门控的电力网络电路和包括该电源门极的半导体器件，以便在以往的标准电池的基础上实现半定制方案，因为具有低功耗。 至少一对第一轨道（1000）包括供应电源电压的电源电压线（1200）和连接到另一个轨道对的基极电压线的虚拟基极电压线（1300），通过第一电源门控电路 1100）。 至少一对第二导轨（2000）包括通过第二电源门控电路（2100）和基极电压线（2300）连接到另一相邻导轨对的电源电压线的虚拟电源电压线（2200） 基极电压。 第一功率选通电路是NMOS（N沟道金属氧化物半导体）晶体管，其响应于睡眠模式控制信号的反相信号切换基极电压线和相邻轨道对的虚拟基极电压线的连接 。

公开(公告)号：KR1020100103195A

公开(公告)日：2010-09-27

申请号：KR1020090021678

申请日：2009-03-13

Applicant: 삼성전자주식회사 ,  한국과학기술원

Inventor： 김형옥 ,  최정연 ,  이봉현 ,  서문준 ,  신영수

IPC: H03K17/687 ,  H03K19/0185 ,  H03K19/0948

CPC classification number: H03K19/0016 ,  H03K19/0013

Abstract: PURPOSE: A power gating circuit and an integrated circuit including the same are provided to reduce the length of wire with respect to a mode controlling signal by utilizing a virtual power voltage as the mode controlling signal. CONSTITUTION: A logic circuit(110) performs a pre-set logic operation. The logic circuit is connected between a first power rail(VDD) and a virtual power rail(VPR). A switching unit(120) selectively connects the virtual power rail with a second power rail(VSS). A retention flip-flop(130) receives the power of the virtual power rail as a controlling signal. The retention flip-flop selectively performs a flip-flop operation or a data retention operation.

Abstract translation: 目的：提供电源门控电路和包括其的集成电路，通过利用虚拟电源电压作为模式控制信号来减少相对于模式控制信号的电线长度。 构成：逻辑电路（110）执行预置逻辑运算。 逻辑电路连接在第一电源轨（VDD）和虚拟电源轨（VPR）之间。 开关单元（120）选择性地将虚拟电源轨与第二电力轨（VSS）连接。 保持触发器（130）作为控制信号接收虚拟电源轨的电力。 保持触发器选择性地执行触发器操作或数据保持操作。

公开(公告)号：KR101612298B1

公开(公告)日：2016-04-14

申请号：KR1020090021678

申请日：2009-03-13

Applicant: 삼성전자주식회사 ,  한국과학기술원

Inventor： 김형옥 ,  최정연 ,  이봉현 ,  서문준 ,  신영수

IPC: H03K17/687 ,  H03K19/0185 ,  H03K19/0948

CPC classification number: H03K19/0016 ,  H03K19/0013

Abstract: 감소된배선길이를가지는파워게이팅회로는로직회로, 스위칭소자및 리텐션플립-플롭을포함한다. 로직회로는 1 전원레일과가상전원레일사이에연결된다. 스위칭소자는모드제어신호에응답하여가상전원레일을제2 전원레일에선택적으로연결한다. 리텐션플립-플롭은가상전원레일의전압을제어신호로서수신하고, 가상전원레일의전압에응답하여플립-플롭동작또는데이터유지동작을선택적으로수행한다.

公开(公告)号：KR1020140050151A

公开(公告)日：2014-04-29

申请号：KR1020120115554

申请日：2012-10-17

Applicant: 삼성전자주식회사 ,  한국과학기술원

Inventor： 서문준 ,  백돈규 ,  신영수 ,  신인섭 ,  김형옥 ,  오충기 ,  전재한 ,  도경태 ,  최정연

IPC: H01L21/00 ,  G06F17/50 ,  H01L21/66

CPC classification number: H01L21/67276 ,  G06F17/50 ,  H01L22/20

Abstract: The present invention relates to a modeling method which estimates delay time and output time of a gate when a body bias voltage is applied. A method of modeling the delay time or the output time of the gate according to the present invention includes a step of selecting a first gate among a plurality of gates; a step of determining the structure of the selected first gate; a step of generating the delay time ratio or the output time ratio of the selected first gate according to the determination result; and a step of calculating the delay time or the output time of a second gate when the body bias voltage is applied based on the delay time or the output time of the second gate among the generated delay time ratio or the output time ratio and the gates. [Reference numerals] (110) First delay time table; (120) Delay time ratio table; (130) Second delay time table

Abstract translation: 本发明涉及一种当施加人体偏置电压时估计门的延迟时间和输出时间的建模方法。 根据本发明的对门的延迟时间或输出时间建模的方法包括在多个门中选择第一门的步骤; 确定所选择的第一门的结构的步骤; 根据确定结果产生所选择的第一门的延迟时间比或输出时间比的步骤; 以及基于所生成的延迟时间比或输出时间比的延迟时间或第二栅极的输出时间来施加施加了体偏置电压时的第二栅极的延迟时间或输出时间的步骤， 。 （附图标记）（110）第一延迟时间表; （120）延迟时间比表; （130）第二延迟时间表