公开(公告)号：KR100993783B1

公开(公告)日：2010-11-11

申请号：KR1020080127184

申请日：2008-12-15

Applicant: 한국과학기술원

Inventor： 김정호 ,  심유정

IPC: H04B5/02 ,  G06K17/00

Abstract: UHF 대역 RFID 리더기에서 DC 오프셋 신호 제거 장치는 샘플링 클락 신호 및 샘플링 제어 신호에 응답하여, 인페이즈(in-phase) 채널 신호를 수신하고 인페이즈 채널 신호의 프리앰블(preamble) 구간 동안에 데이터 레이트(data rate)의 정수배에 해당하는 주파수로 프리앰블 신호를 샘플링하고 샘플링된 값들의 제 1 누적값 및 제 1 샘플링 횟수에 기초하여 DC 오프셋이 제거된 인페이즈 채널 신호를 제공하는 제 1 DC 오프셋 제거부 및 샘플링 클락 신호 및 샘플링 제어 신호에 응답하여, 쿼드러처페이즈(quadrature-phase) 채널 신호를 수신하고 쿼드러처페이즈 채널 신호의 프리앰블 구간 동안에 데이터 레이트의 정수배에 해당하는 주파수로 프리앰블 신호를 샘플링하고 샘플링된 값들의 제 2 누적값 및 제 2 샘플링 횟수에 기초하여 DC 오프셋이 제거된 쿼드러처페이즈 채널 신호를 제공하는 제 2 DC 오프셋 제거부를 포함한다.

公开(公告)号：KR1020100068729A

公开(公告)日：2010-06-24

申请号：KR1020080127184

申请日：2008-12-15

Applicant: 한국과학기술원

Inventor： 김정호 ,  심유정

IPC: H04B5/02 ,  G06K17/00

CPC classification number: H04B5/0062 ,  H04B1/10 ,  H04B1/16

Abstract: PURPOSE: An apparatus for removing DC offset in a UHF(Ultra High Frequency) RFID(Radio Frequency ID) reader, an RFID reader including the same, and a method for removing the DC offset are provided to reduce reader errors while effectively removing a DC offset signal. CONSTITUTION: A first DC(Direct Current) offset remover(510) offers an in-phase channel signal in which DC offset is removed and receives the phase channel signal according to a sampling control signal and a sampling clock signal. A second DC offset sremover(520) offers a quadrature-phase channel signal in which the DC offset is removed receives the quadrature-phase channel signal.

Abstract translation: 目的：提供一种用于去除超高频（超高频）RFID（射频识别码）读取器，包括其的RFID读取器的DC偏移的装置和用于去除DC偏移的方法，以减少读取器错误，同时有效地去除DC 偏移信号。 构成：第一DC（直流）偏移去除器（510）提供同相信道信号，其中DC偏移被去除，并且根据采样控制信号和采样时钟信号接收相位通道信号。 第二DC偏移抑制（520）提供正交相位通道信号，其中去除DC偏移接收正交相位通道信号。

公开(公告)号：KR100865335B1

公开(公告)日：2008-10-27

申请号：KR1020070064854

申请日：2007-06-29

Applicant: 한국과학기술원

Inventor： 김정호 ,  심유정

IPC: H04B5/02 ,  H04B5/00 ,  G06K17/00

CPC classification number: H04B5/0062 ,  H04B1/0007 ,  H04B1/10 ,  H04B1/16 ,  H04B5/02

Abstract: A digital signal restoring circuit and a digital signal restoring method are provided to offer a clock signal for controlling a range that an analog signal is converted into a digital signal in a desired restoration range, thereby restoring and outputting only a digital signal in a desired range. A digital signal restoring circuit(100) includes a clock signal generator(110), an ADC(Analog to Digital Converter) unit(120), and a sampling unit(130). The clock signal generator provides a clock signal(SIG3) based on an input signal(Vin), and first and second threshold values(VDD/2+Va,VDD/2-Va). The ADC unit provides a first digital signal(SIG4) based on a reference value(VDD/2) corresponding to an average value of the first and second threshold values and the input signal. The sampling unit is synchronized with the clock signal to sample the first digital signal to output a second digital signal(SIG5).

Abstract translation: 提供数字信号恢复电路和数字信号恢复方法以提供用于控制模拟信号被转换成期望恢复范围内的数字信号的范围的时钟信号，从而仅恢复并输出期望范围内的数字信号 。 数字信号恢复电路（100）包括时钟信号发生器（110），ADC（模数转换器）单元（120）和采样单元（130）。 时钟信号发生器基于输入信号（Vin）和第一和第二阈值（VDD / 2 + Va，VDD / 2-Va）提供时钟信号（SIG3）。 ADC单元基于对应于第一和第二阈值和输入信号的平均值的参考值（VDD / 2）提供第一数字信号（SIG4）。 采样单元与时钟信号同步，对第一数字信号采样以输出第二数字信号（SIG5）。

公开(公告)号：KR101010596B1

公开(公告)日：2011-01-24

申请号：KR1020090116730

申请日：2009-11-30

Applicant: 한국과학기술원

Inventor： 김정호 ,  심유정

IPC: H04B3/04 ,  H04B1/10 ,  H04B1/66

CPC classification number: H04B3/04 ,  H04L25/03878

Abstract: PURPOSE: An equalizer and a communications device having wide bandwidth are provided to make the equalizer small without consuming power. CONSTITUTION: A terminating register is connected between the end part of stub and a ground plane arranged in the bottom surface of a dielectric layer. A defected ground structure is located on a ground plane. The defected ground structure has the shape in which the ground plane of the vertical downward is partially eliminated. The characteristic impedance of the stub is bigger than the impedance of the terminating resistance. The characteristic impedance of stub is bigger than the characteristic impedance of the transmission line.

Abstract translation: 目的：提供均衡器和具有宽带宽的通信设备，以使均衡器小而不消耗电力。 构成：终端寄存器连接在短截线端部与布置在电介质层底面的接地面之间。 缺陷的地面结构位于地平面上。 缺陷的地面结构具有垂直向下的接地平面被部分消除的形状。 短截线的特征阻抗大于端接电阻的阻抗。 短截线的特征阻抗大于传输线的特性阻抗。

公开(公告)号：KR100783735B1

公开(公告)日：2007-12-07

申请号：KR1020060119282

申请日：2006-11-29

Applicant: 한국과학기술원

Inventor： 김정호 ,  심유정

IPC: H04B1/40 ,  H04B5/02

CPC classification number: H04B5/0062 ,  G06K7/10297 ,  G06K7/10386 ,  H04B5/02

Abstract: An RFID(Radio Frequency Identification) reader is provided to separate a Tx circuit or a power amplifier from a basic circuit so that noise by a signal from the Tx circuit or the power amplifier can have little effect on the basic circuit. An RFID reader(200) comprises a Tx circuit(220) and a basic circuit(210). The Tx circuit(220) creates the first signal containing power to be sent to an RFID tag. The basic circuit(210), spatially separated from the Tx circuit on an identical package, receives the second signal from the RFID tag and processes it. In addition, the RFID reader comprises a Tx/Rx-combined antenna for the transmission of the first signal and the reception of the second signal.

Abstract translation: 提供RFID（射频识别）读取器以将Tx电路或功率放大器与基本电路分离，使得来自Tx电路或功率放大器的信号的噪声对基本电路几乎没有影响。 RFID读取器（200）包括Tx电路（220）和基本电路（210）。 Tx电路（220）产生包含发送到RFID标签的功率的第一信号。 在相同封装上与Tx电路在空间上分离的基本电路（210）从RFID标签接收第二信号并对其进行处理。 此外，RFID读取器包括用于传输第一信号和接收第二信号的Tx / Rx组合天线。

公开(公告)号：KR100771146B1

公开(公告)日：2007-10-29

申请号：KR1020060120195

申请日：2006-11-30

Applicant: 한국과학기술원

Inventor： 김정호 ,  박종배 ,  심유정

IPC: H01L23/58 ,  H01L23/60

CPC classification number: H01L2224/33 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L23/552 ,  H01L23/142 ,  H01L23/522 ,  H01L2924/00012

Abstract: A system in package is provided to suppress high-frequency switching noise and electromagnetic interference effectively by using the single layer capacitor of high self resonant frequency and high capacitor. At least one integrated circuit chip is mounted on a main chip pad(11), and a ground plane(12) is formed under the main chip pad to provide the integrated circuit chip with a ground potential. A power plane(13) is spaced apart from the ground plane to supply a power potential to the integrated circuit chip. A single layer capacitor chip(15) is composed of two metal plates and a high-k material filled between the plates, and is interposed between the ground plane and the power plane so that the two metal plates are electrically connected to the ground plane and the power plane.

Abstract translation: 提供一种封装体系，通过使用高自谐振频率和高电容的单层电容器有效抑制高频开关噪声和电磁干扰。 至少一个集成电路芯片安装在主芯片焊盘（11）上，并且在主芯片焊盘下形成接地平面（12），以为集成电路芯片提供接地电位。 电源平面（13）与接地平面间隔开，以向集成电路芯片供电。 单层电容器芯片（15）由两个金属板和填充在板之间的高k材料组成，并且被插入在接地平面和电源平面之间，使得两个金属板电连接到接地平面， 电力平面。