公开(公告)号：KR100379284B1

公开(公告)日：2003-04-10

申请号：KR1020000053215

申请日：2000-09-07

Applicant: 한국과학기술원

Inventor： 전재호 ,  박영서 ,  박현욱

IPC: H03M7/40

Abstract: PURPOSE: A high-speed variable length decoder using plane partition is provided to improve a total speed of a variable length decoder by performing simultaneously a parallel matching process of decoding data and an input process of a decoding code length signal. CONSTITUTION: Two input planes(11) are used for receiving data. The input planes(11) are separated to each other. A programmable logic array(5,5') is connected with a one input plane of the separated input planes(11). A subtracter(19) and an adder(20) are connected with an output terminal of the programmable logic array(5,5'). Code length signals of decoded information of a programmable logic array(5,5') are inputted into each input plane(11) and the subtracter(19), respectively. The remaining bit stream is checked by using the code length signal provided from the programmable logic array(5,5'). A supply control operation of a decoding bit stream is performed by using the code length signal provided from the programmable logic array(5,5').

Abstract translation: 目的：提供一种使用平面分区的高速可变长度解码器，通过同时执行解码数据的并行匹配处理和解码码长信号的输入处理来提高可变长度解码器的总速度。 构成：两个输入平面（11）用于接收数据。 输入平面（11）彼此分离。 可编程逻辑阵列（5,5'）与分离的输入平面（11）的一个输入平面连接。 减法器（19）和加法器（20）与可编程逻辑阵列（5,5'）的输出端连接。 可编程逻辑阵列（5,5'）的解码信息的码长信号分别被输入到每个输入平面（11）和减法器（19）。 通过使用从可编程逻辑阵列（5,5'）提供的码长信号来检查剩余的比特流。 通过使用从可编程逻辑阵列（5,5'）提供的码长信号来执行解码比特流的供应控制操作。

公开(公告)号：KR1020020019854A

公开(公告)日：2002-03-13

申请号：KR1020000053215

申请日：2000-09-07

Applicant: 한국과학기술원

Inventor： 전재호 ,  박영서 ,  박현욱

IPC: H03M7/40

CPC classification number: H04N19/13 ,  H03M7/40 ,  H04N19/91

Abstract: PURPOSE: A high-speed variable length decoder using plane partition is provided to improve a total speed of a variable length decoder by performing simultaneously a parallel matching process of decoding data and an input process of a decoding code length signal. CONSTITUTION: Two input planes(11) are used for receiving data. The input planes(11) are separated to each other. A programmable logic array(5,5') is connected with a one input plane of the separated input planes(11). A subtracter(19) and an adder(20) are connected with an output terminal of the programmable logic array(5,5'). Code length signals of decoded information of a programmable logic array(5,5') are inputted into each input plane(11) and the subtracter(19), respectively. The remaining bit stream is checked by using the code length signal provided from the programmable logic array(5,5'). A supply control operation of a decoding bit stream is performed by using the code length signal provided from the programmable logic array(5,5').

Abstract translation: 目的：提供使用平面分区的高速可变长度解码器，通过同时进行解码数据的并行匹配处理和解码码长信号的输入处理来提高可变长度解码器的总速度。 构成：两个输入平面（11）用于接收数据。 输入平面（11）彼此分离。 可编程逻辑阵列（5,5'）与分离的输入平面（11）的一个输入平面连接。 减法器（19）和加法器（20）与可编程逻辑阵列（5,5'）的输出端子连接。 可编程逻辑阵列（5,5'）的解码信息的码长信号分别输入到每个输入平面（11）和减法器（19）中。 通过使用从可编程逻辑阵列（5,5'）提供的码长信号来检查剩余比特流。 通过使用从可编程逻辑阵列（5,5'）提供的码长信号来执行解码比特流的电源控制操作。