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公开(公告)号：KR1020050065893A
公开(公告)日：2005-06-30
申请号：KR1020030097053
申请日：2003-12-26
Applicant: 한국전자통신연구원
IPC: H01L31/12
Abstract: 본 발명은 광소자에 관한 발명이다. 특히, 광도파로형 광검출기와 전치 증폭단용 이종접합 바이폴라 트랜지스터의 일체형 광전 집적 수신 소자 및 그 제조 방법에 관한 것이다.
상술한 목적을 달성하기 위한 기술적 수단으로서, 본 발명의 제 1 측면은 반도체 기판, 상기 반도체 기판 위에 위치하고, 광검출기의 양자효율을 증가시키고, N형 반도체인 제 1 코어층, 상기 제 1 코어층 위에 위치하고, 진성 반도체인 광흡수층, 상기 광흡수층 위에 위치하고, 광검출기의 양자효율을 증가시키고, P형 반도체인 제 2 코어층, 및 상기 제 2 코어층 위에 위치하는 클래드층을 포함하는 광검출기를 제공한다. 또한 이를 포함하는 광전 집적 수신 소자 및 그 제조 방법을 제공한다.
본 발명에 의한 광검출기, 광전 집적 수신 소자 및 그 제조 방법은 초고속 응답 특성을 갖고, 초고주파 증폭이 가능하다는 장점이 있다.-
公开(公告)号：KR1020020054108A
公开(公告)日：2002-07-06
申请号：KR1020000082803
申请日：2000-12-27
Applicant: 한국전자통신연구원
IPC: H01L21/336
CPC classification number: H01L29/66431 , H01L29/665 , H01L29/66545 , H01L29/7782
Abstract: PURPOSE: A germanium silicon modulation doped field effect transistor(MODFET) using a metal-oxide layer gate is provided to improve a linear characteristic of a hetero-junction complementary metal oxide semiconductor(CMOS), by using a hetero junction structure of SiGe/C and SiGe/Si. CONSTITUTION: A buffering thin film made of silicon is grown on a silicon substrate. A SiGe channel layer and a silicon cap layer are formed on the buffering thin film. A low temperature buffer layer and a SiGe buffer layer are grown on the silicon substrate by a low temperature process. A defect caused by lattice mismatch applied from the silicon substrate to an epi layer is artificially formed.
Abstract translation: 目的：提供使用金属氧化物层栅极的锗硅调制掺杂场效应晶体管（MODFET），以通过使用SiGe / C的异质结结构来改善异质结互补金属氧化物半导体（CMOS）的线性特性 和SiGe / Si。 构成：在硅衬底上生长由硅制成的缓冲薄膜。 在缓冲薄膜上形成SiGe沟道层和硅覆盖层。 通过低温工艺在硅衬底上生长低温缓冲层和SiGe缓冲层。 人造地形成从硅衬底施加到外延层的晶格失配引起的缺陷。
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公开(公告)号：KR1020010038202A
公开(公告)日：2001-05-15
申请号：KR1019990046086
申请日：1999-10-22
Applicant: 한국전자통신연구원
IPC: H01L21/31
Abstract: PURPOSE: A method of growing a semiconductor thin film is to deposit amorphous silicon dopped high concentration impurity on a natural oxide film and accelerates decomposition of the oxide film with heat treatment, thereby reducing annealing temperature and increasing crystallizing ability and the decomposition of the oxide. CONSTITUTION: An amorphous silicon film(32) dopped high concentration impurity is deposited on a natural oxide(34) film of a substrate. The substrate deposited on the amorphous silicon film is annealed so that the natural oxide film is resolved and mono-crystallized. After mono-crystallizing the amorphous silicon, the annealing temperature is lowered and then a mono-crystalline silicon thin film(33) is deposited. In the depositing process, the amorphous silicon has a thickness of at least 20nm. The depositing process is performed at a temperature of below 500 deg.C. The impurity is an n type or a p type such as B, P, As and Sb. The annealing process is performed for few seconds at a temperature of at least 700 deg.C or more. The impurity is implanted with a concentration of 1x10¬19/cm8-5x10¬22/cm.
Abstract translation: 目的：生长半导体薄膜的方法是在自然氧化膜上沉积非晶硅掺杂的高浓度杂质，并通过热处理加速氧化膜的分解，从而降低退火温度，提高结晶能力和氧化物分解。 构成：将掺杂高浓度杂质的非晶硅膜（32）沉积在衬底的天然氧化物（34）膜上。 将沉积在非晶硅膜上的衬底退火，使得天然氧化物膜被分离并单结晶。 在非晶硅单结晶之后，退火温度降低，然后沉积单晶硅薄膜（33）。 在沉积过程中，非晶硅的厚度至少为20nm。 沉积过程在低于500℃的温度下进行。 杂质是n型或p型，如B，P，As和Sb。 退火处理在至少700℃以上的温度下进行几秒钟。 以1×10 19 / cm 8 -5×10 21 / cm的浓度注入杂质。
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公开(公告)号：KR1020170089341A
公开(公告)日：2017-08-03
申请号：KR1020160009629
申请日：2016-01-26
Applicant: 한국전자통신연구원
IPC: H01L31/09 , H01P7/00 , G02B1/10 , G01J1/04 , H01L31/0352
CPC classification number: G02B6/29341 , G01D5/35319 , G02B6/12007 , G02B6/124 , G02B6/136 , G02B6/32 , G02B2006/12097 , G02B2006/12104 , G02B2006/12138 , H01S5/0028 , H01S5/026 , H01S5/1075 , H01S5/125 , H01S5/22 , H01S5/3013 , H01S5/4012 , H01S5/4031 , H01S5/4068
Abstract: 본발명은공진기및 이를이용한광센서에관한것으로, 위스퍼링갤러리모드(Whispering Gallery Mode; WGM)를이용한반원형공진기및 이를이용한광센서에관한것이다. 이에따른본 발명은, 진행되는광의이득에의하여레이저발진을일으키는활성층의도파로인상기활성영역이반원형또는반링형으로깊이식각되는것을특징으로하는공진기및 이를이용한광센서에관한것이다.
Abstract translation: 本发明涉及一种半圆形腔，以及与使用该光学传感器;（WGM回音壁模式）本发明涉及一种谐振器和使用同样的，回音壁模式的光学传感器。 由光学传感器的光增益在继续本发明是在活性层使用的谐振器，以使激光振荡的波导管的有源区和这一点，其特征在于，蚀刻深度的半圆形或半环形按照。
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公开(公告)号：KR100491089B1
公开(公告)日：2005-05-24
申请号：KR1020020077325
申请日：2002-12-06
Applicant: 한국전자통신연구원
IPC: H01L29/737
Abstract: 기판; 기판 위에 형성되어 있는 컬렉터 층; 컬렉터 층 위에 형성되어 있는 베이스 층; 베이스 층 위에 패턴화 되어 형성되어 있는 이미터 층 패턴; 이미터 층 패턴 위에 형성되어 있는 이미터 금속 패턴; 베이스 층 위에 형성되어 있고, 이미터 금속 패턴과 소정 간격 이격되어 있는 베이스 금속 패턴; 이미터 금속 패턴과 상기 베이스 금속 패턴의 사이에 형성되어 있는 절연 측벽을 포함하는 이종 접합 바이폴라 트랜지스터.
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Patent Agency Ranking
公开(公告)号：KR100385857B1
公开(公告)日：2003-06-02
申请号：KR1020000082803
申请日：2000-12-27
Applicant: 한국전자통신연구원
IPC: H01L21/336
CPC classification number: H01L29/66431 , H01L29/665 , H01L29/66545 , H01L29/7782
Abstract: There is disclosed a method for fabricating a SiGe MODFET device using a metal oxide film. The present invention provides a SiGe MODFET device with improved operation speed and reduced non-linear operation characteristic caused in a single channel stricture devices, by increasing the mobility of the carriers in the SiGe MODEFT having a metal-oxide gate, and method of fabricating the same. In order to accomplish the above object, the present invention grows a silicon buffer layer and a SiGe buffer layer on a silicon substrate by low-temperature process, so that defects caused by the mismatch of the lattice constants being applied to the epitaxial layer from the silicon substrate are constrained in the buffer layered formed by the low-temperature process.
Abstract translation: 公开了一种使用金属氧化物膜制造SiGe MODFET器件的方法。 本发明提供了一种通过增加具有金属氧化物栅极的SiGe MODEFT中的载流子的迁移率而提高了在单沟道狭窄器件中引起的操作速度和降低的非线性操作特性的SiGe MODFET器件以及制造 相同。 为了实现上述目的，本发明通过低温工艺在硅衬底上生长硅缓冲层和SiGe缓冲层，从而由晶格常数失配引起的外延层 硅衬底被限制在由低温工艺形成的缓冲层中。
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公开(公告)号：KR100347519B1
公开(公告)日：2002-08-07
申请号：KR1019990046086
申请日：1999-10-22
Applicant: 한국전자통신연구원
IPC: H01L21/31
Abstract: 본발명은반응성가스를사용하는표면처리과정이나고온에서수소분위기로열처리하는과정이필요없는반도체박막을저온성장하는방법에관한것이다. 이러한반도체박막을저온성장하는방법은, 자연산화막이자연생성된기판위에단결정실리콘반도체박막을성장하는방법에있어서, 상기자연산화막이생성된기판위에불순물이도핑된비정질실리콘박막을증착하는증착단계와, 상기비정질실리콘박막이증착된기판을열처리하여상기자연산화막이분쇄되면서단결정화되도록하는열처리단계, 및상기비정질실리콘박막의단결정화후 온도를낮추어단결정의실리콘박막을증착하는단결정박막증착단계를포함한다.
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公开(公告)号：KR1020020029190A
公开(公告)日：2002-04-18
申请号：KR1020000060004
申请日：2000-10-12
Applicant: 한국전자통신연구원
IPC: H01L21/205
CPC classification number: H01L21/67757 , C23C16/4401 , C23C16/46 , C23C16/54 , C30B25/02
Abstract: PURPOSE: A vertical ultra-vacuum chemical deposition apparatus is provided to sufficiently improve productivity, by growing a high-quality thin film at a low pressure of 10¬-3 Torr and a low temperature of 500 deg.C and by simultaneously disposing 50 wafers. CONSTITUTION: A growth chamber(100) maintains uniformity of growth of an epitaxial layer at a high vacuum and minimizes heat transferred from a wafer, having a quartz tube of a dual structure. A wafer transfer chamber(200) includes a vertical transfer apparatus for vertically transferring the wafer in which the epitaxial growth layer is formed, connected to the lower portion of the growth chamber. A buffer chamber(300) prevents stress from being applied to a transfer gear by a pressure difference with a wafer transfer chamber in vertically transferring the wafer, installed in the lower portion of the wafer transfer chamber. A loadlock chamber(400) reduces contamination from the exterior in growing the epitaxial growth layer and horizontally transfers the wafer having the epitaxial growth layer to the exterior, connected to a side of the wafer transfer chamber.
Abstract translation: 目的：提供一种立式超真空化学沉积装置，通过在10 -3 Torr低温和500摄氏度的低压下生长高质量的薄膜，同时配置50个晶片，以充分提高生产率 。 构成：生长室（100）在高真空下保持外延层的生长均匀性，并使具有双重结构的石英管的从晶片传递的热量最小化。 晶片传送室（200）包括垂直传送装置，用于垂直传送其中形成外延生长层的晶片，连接到生长室的下部。 缓冲室（300）通过与安装在晶片传送室的下部垂直传送晶片的晶片传送室的压差来防止施加到传送齿轮的应力。 负载锁定室（400）在生长外延生长层时减少来自外部的污染物，并将具有外延生长层的晶片水平地传递到外部，连接到晶片传送室的一侧。
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公开(公告)号：KR1020040049527A
公开(公告)日：2004-06-12
申请号：KR1020020077325
申请日：2002-12-06
Applicant: 한국전자통신연구원
IPC: H01L29/737
Abstract: PURPOSE: A HBT(hetero-junction bipolar transistor) is provided to embody low metal contact resistance and base resistance and improve a cut-off frequency and maximum resonant frequency by forming an outer base layer of a superhigh density through an ion implantation process. CONSTITUTION: A substrate(1) is prepared. A collector layer(3) is formed on the substrate. A base layer is formed on the collector layer. An emitter layer pattern is patterned on the base layer. An emitter metal pattern(6a) is formed on the emitter layer pattern. A base metal pattern(6b) is formed on the base layer, separated from the emitter metal pattern by a predetermined interval. An insulation sidewall(7a) is formed between the emitter metal pattern and the base metal pattern.
Abstract translation: 目的：通过离子注入工艺形成超高密度外基层，提供HBT（异质结双极晶体管），以实现低金属接触电阻和基极电阻，并提高截止频率和最大谐振频率。 构成：制备基材（1）。 在基板上形成集电体层（3）。 在集电体层上形成基层。 发射极层图案在基底层上图案化。 发射极金属图案（6a）形成在发射极层图案上。 在基底层上形成贱金属图案（6b），与发射极金属图案分开预定间隔。 在发射极金属图案和基底金属图案之间形成绝缘侧壁（7a）。
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