公开(公告)号：KR100317991B1

公开(公告)日：2001-12-22

申请号：KR1020000003493

申请日：2000-01-25

Applicant: 한국전자통신연구원

Inventor： 도한철 ,  이형호 ,  이형섭

IPC: H04L12/28

Abstract: 본 발명은 기가비트 이더넷 기반 라우터에서의 패킷 포워딩 처리에 관한 것으로서, 기가비트 이더넷 시스템에서 기가비트 속도의 트래픽을 만족하는 빠른 포워딩을 구현하기 위해 기가비트 와이어스피드(wired-speed)를 보장하는 룩업의 결과에 대해 듀얼 포트메모리를 버퍼로 사용하고 하드웨어 방법에 의한 병렬처리형 패킷 포워딩 처리를 함으로써 실시간의 패킷 포워딩을 가능하게 하여 라우터 시스템 성능을 향상시키는 병렬처리형 3계층 패킷 포워딩 처리 방법 및 장치를 제공한다.
본 발명은 프로세싱 시간을 단축하여 기가비트 속도처리가 가능하게 하고, 룩업의 결과에 의한 패킷처리를 프로세서의 개입없이 일정 시간지연내로 보장할 수 있으며, 또 입력 프로세싱과는 별도로 병렬 처리하므로 회로의 간단화를 통한 비용 절감의 효과가 있다.

公开(公告)号：KR1020010076079A

公开(公告)日：2001-08-11

申请号：KR1020000003493

申请日：2000-01-25

Applicant: 한국전자통신연구원

Inventor： 도한철 ,  이형호 ,  이형섭

IPC: H04L12/28

CPC classification number: H04L45/66 ,  H04L45/02 ,  H04L45/04

Abstract: PURPOSE: A parallel process type 3-layer packet forwarding processing method in a gigabit Ethernet-based router and an apparatus thereof are provided to simplify a circuit and save a cost by independently perform a parallel process in the same buffer using a dual port memory as the buffer when temporally storing a packet and correcting header information and simultaneously processing the packet by a look-up result without a processor. CONSTITUTION: A packet routing central controller(203) controls an entire routing procedure irrespective of a processor. A look-up controller(204) searches a look-up to a destination IP address through a look-up table(205) by the request of the packet routing central controller(203). The look-up table(205) stores information to an IP address. A packet write controller(202) designates a storing point of an input packet. A packet correction controller(206) designates a packet correction position by a look-up result. A packet read controller(207) designates a packet address read to a host. A pointer intervener(208) intervenes between a correction write point and a read point inputted from the packet read controller(207). A buffer(209) stores an inputted packet, and is a dual port memory for performing a read and write of a common data in an inter-different port.

Abstract translation: 目的：提供一种基于千兆位以太网的路由器及其装置中的并行处理类型3层分组转发处理方法，以便通过使用双端口存储器独立地在同一缓冲器中执行并行处理来简化电路并节省成本 暂时存储分组并且校正报头信息并且在没有处理器的情况下通过查找结果同时处理分组的缓冲器。 构成：分组路由中央控制器（203）控制整个路由过程，而与处理器无关。 查找控制器（204）通过分组路由中央控制器（203）的请求通过查找表（205）搜索到目的地IP地址的查找。 查找表（205）将信息存储到IP地址。 分组写入控制器（202）指定输入分组的存储点。 分组校正控制器（206）通过查找结果指定分组校正位置。 分组读取控制器（207）指定向主机读取的分组地址。 指针交换器（208）介于校正写入点和从分组读取控制器（207）输入的读取点之间。 缓冲器（209）存储输入的分组，并且是用于在不同端口中执行公共数据的读取和写入的双端口存储器。

公开(公告)号：KR1020010063670A

公开(公告)日：2001-07-09

申请号：KR1019990061250

申请日：1999-12-23

Applicant: 한국전자통신연구원

Inventor： 김기민 ,  도한철 ,  이형호 ,  이승수

IPC: H04L7/033

Abstract: PURPOSE: An apparatus for synchronizing a data stream received with two phase input clocks with a transmission clock is provided which synchronizes a 125MHz data stream synchronized with two reception clocks with 125MHz transmission clock to make a new data stream and controls circuits of a transceiver with the transmission clock. CONSTITUTION: A synchronizing apparatus includes a data stream divider(41) for synchronizing a data stream received from a physical medium with the first reception clock and the second reception clock that is the inversion state of the first reception clock to divide the data stream into two data streams. The synchronizing apparatus further has a data stream selector(42) for synchronizing the two data streams using a transmission clock asynchronous with the first and second reception clocks to generate two data streams, and a combiner(43) for combining the two data streams to transmit the data stream synchronized with the transmission clock.

Abstract translation: 目的：提供一种用于将具有两个相位输入时钟的数据流与传输时钟同步的装置，其将与125MHz传输时钟的两个接收时钟同步的125MHz数据流同步以产生新的数据流，并且控制收发器的电路 传输时钟。 构成：同步装置包括用于使从物理介质接收的数据流与第一接收时钟同步的数据流分配器（41）和作为第一接收时钟的反转状态的第二接收时钟，以将数据流划分为两个 数据流。 同步装置还具有数据流选择器（42），用于使用与第一和第二接收时钟异步的传输时钟同步两个数据流以产生两个数据流;以及组合器（43），用于组合两个数据流以传输 数据流与传输时钟同步。

公开(公告)号：KR100258068B1

公开(公告)日：2000-06-01

申请号：KR1019970071635

申请日：1997-12-22

Applicant: 한국전자통신연구원 ,  주식회사 케이티

Inventor： 도한철 ,  송주빈

IPC: H04L12/24

Abstract: PURPOSE: A method for interworking an upload/down between control boards is provided to increase a reliability of a synchronous circuit distribution device by interworking a precedence control board and a subordinate control board. CONSTITUTION: On the occasion of a mounting and a detachment of a central concentrating control board(2), the central concentrating control board(2) requires present state information of subordinate control boards(3) in the time of the mounting(13). The subordinate control boards(3) reports the present state information of subordinate control boards(3,14). The central concentrating control board(2) transmits device information to each of the subordinate control boards(3,16). On the occasion of re-connection of the central concentrating control board(2) and a user interface(1), the user interface requires the present state information of the central concentrating control board(2,18). The central concentrating control board(2) reports the present state information(19). The user interface transmits the device information(21). On the occasion of a mounting and a detachment of the subordinate control board(3), the subordinate control board(3) performs an initialized routine. When there is no response of the central concentrating control board(2) pertinent to the initialized routine, the subordinate control board(3) operates in an independent operation mode. On the contrary, when there is the response of the central concentrating control board(2) pertinent to the initialized routine, the subordinate control board(3) operates in an interworking mode. After finishing an initialization, the subordinate control board(3) transmits an initialization finish message to the central concentrating control board(2,12). After this, the subordinate control board(3) transmits the present state information to the central concentrating control board(2,14). Next, the central concentrating control board(2) transmits download information to the subordinate control board(3,16), and the subordinate control board(3) performs a construction and a control of related boards.

Abstract translation: 目的：提供一种在控制板之间互联上下传的方法，通过互联优先控制板和从属控制板来提高同步电路分配设备的可靠性。 构成：在中央集中控制板（2）的安装和拆卸的情况下，中央集中控制板（2）在安装时需要下属控制板（3）的状态信息（13）。 下属控制板（3）报告下属控制板（3,14）的当前状态信息。 中央集中控制板（2）向每个下属控制板（3,16）发送设备信息。 在中央集中控制板（2）和用户界面（1）的重新连接的情况下，用户界面需要中央集中控制板（2,18）的当前状态信息。 中央集中控制板（2）报告当前状态信息（19）。 用户界面发送设备信息（21）。 在下位控制板（3）的安装和拆卸的情况下，从属控制板（3）执行初始化程序。 当与初始化程序相关的中央集中控制板（2）没有响应时，下属控制板（3）以独立的操作模式工作。 相反，当与中央集中控制板（2）有关于初始化程序的响应时，下级控制板（3）以交互模式工作。 完成初始化后，下级控制板（3）向中央集中控制板（2,12）发送初始化完成消息。 此后，下属控制板（3）将当前状态信息发送到中央集中控制板（2,14）。 接下来，中央集中控制板（2）向下属控制板（3,16）发送下载信息，下属控制板（3）进行相关板的构造和控制。

公开(公告)号：KR100384895B1

公开(公告)日：2003-05-22

申请号：KR1019990039919

申请日：1999-09-16

Applicant: 한국전자통신연구원

Inventor： 도한철 ,  이왕환 ,  이형섭

IPC: H04L12/935

Abstract: PURPOSE: A device and a method for a multi-layer parallel processing lookup in a communication system are provided to apply a CAM(Content Addressable Memory) to simultaneously and independently process the lookup of a 2-layer MAC(Medium Access Control) address and a 3-layer IP(Internet Protocol) address in order to implement a fast lookup satisfying a gigabit speed of traffic. CONSTITUTION: An MAC(Medium Access Control,41) performs protocol processing for a gigabit speed of signal received from an Ethernet physical medium, and delivers a packet frame inside a system through an inner receiving FIFO(First-In-First-Out). In a lookup control unit(42) an address recognizer(421) latches a header of a gigabit capacity of packet data frame received from the receiving FIFO of the MAC(41) in real time, to extract necessary information. A 2-layer lookup controller(422) controls a 2-layer CAM(Content Addressable Memory)(423) and searches output network information, to obtain lookup information on an MAC address processed in a 2-layer among the extracted information. A 3-layer lookup controller(424) controls a 3-layer CAM(425) and searches output network information, to obtain lookup information on an IP(Internet Protocol) address processed in a 3-layer among the extracted information. A forwarding transmission unit(426) transmits the output network information obtained from the 2-layer and 3-layer lookup controllers(422,424) to a forwarding unit(43).

Abstract translation: 目的：提供一种用于在通信系统中进行多层并行处理查找的设备和方法，以应用CAM（内容可寻址存储器）以同时且独立地处理2层MAC（媒体访问控制）地址的查找和 一个3层IP（互联网协议）地址，以实现满足千兆速度流量的快速查找。 构成：MAC（媒体访问控制41）对从以太网物理介质接收到的千兆速度的信号执行协议处理，并通过内部接收FIFO（先进先出）在系统内传送分组帧。 在查找控制单元（42）中，地址识别器（421）实时地锁存从MAC（41）的接收FIFO接收的千兆位容量的分组数据帧的报头，以提取必要的信息。 2层查找控制器（422）控制2层CAM（内容可寻址存储器）（423）并搜索输出网络信息，以获得关于在所提取的信息中的2层中处理的MAC地址的查找信息。 3层查找控制器（424）控制3层CAM（425）并搜索输出网络信息，以获得关于在所提取的信息中的3层中处理的IP（互联网协议）地址的查找信息。 转发传输单元（426）将从2层和3层查找控制器（422,424）获得的输出网络信息传输到转发单元（43）。

公开(公告)号：KR100358353B1

公开(公告)日：2002-10-25

申请号：KR1019990062388

申请日：1999-12-27

Applicant: 한국전자통신연구원

Inventor： 이형섭 ,  도한철 ,  이형호 ,  이승수 ,  송상섭

IPC: H04L12/26

Abstract: 본발명은 8B/10B 코딩방법에있어서수신부에서수신된데이터열의에러를검출할수 있는러닝디스패리티(RD; Running Disparity) 검출장치및 방법에관한것으로, 종래의 5B(bit)/6B(bit) 의디스패리티를구한후 이디스패리티결과와나머지 4 비트데이터의 3B/4B 코딩의디스패리티를더하여 8B/10B 의디스패리티를구하는순차적인디스패리티발생방법으로는기가비트이더넷과같은초고속시스템에적용할수 없었던문제점을해결하고자하는것이다. 본발명은바이트단위클럭을이용하여 10 비트데이터열에서직접 8B/10B 의디스패리티위반데이터열을추출하는방법을제안한다. 즉, 본발명은 10 비트열에서 '1'과 '0'의비트수를계산하여, '1'이많은경우 '포지티브', '0'이많은경우 '네가티브', '1'과 '0'의비트수가동일한경우 '동일'로나누어처리하고, 위반데이터열을추출하는 RD 에러검출방법은이전의 RD 값을계산하고, 계산된 PRE_RD 값과현재의데이터열인 RX_CDGR(n+1)의 6 비트열의 '1'의개수(RD6_ONE)와 4 비트열의 '1'의개수(RD4_ONE)의계산된값을비교하는방법을채택함으로써, 10 비트데이터열에서직접디스패리티위반을추출할수 있으며, 바이트단위의클럭하나만을사용하므로, 기가비트이더넷과같은고속의시스템에도적용이가능하다.

公开(公告)号：KR1020010064226A

公开(公告)日：2001-07-09

申请号：KR1019990062376

申请日：1999-12-27

Applicant: 한국전자통신연구원

Inventor： 안석순 ,  도한철 ,  이형호

IPC: G06F17/30

Abstract: PURPOSE: A method for compressing, searching and inserting new items considering memory hierarchy structure is provided to increase a velocity of a multiple searching tree by using one pointer in one node, thereby identifying (the number of a key x the size of the key + pointer size) with a size of a cache line. CONSTITUTION: If a new item process is started(S601), a position to be appended by a new item is searched(S602), and the new item is appended to a node thereof. In addition, if the node is full, a medium value is appended to a parent node, and child nodes are divided into and inserted in two consecutive memories(S603). A process to be appended in the parent node is identified with a method to be appended to the current node. If a specific node deletion process is started(S604), a position to be deleted is searched(S605), and the corresponding item is deleted from the corresponding node(S606). As the result of the deletion, if the number of items of the corresponding node is decreased less than the half thereof, the node is integrated to an adjacent node, and the two consecutive memories having children of two nodes are integrated as one consecutive memory. If two adjacent nodes are integrated caused by a deletion, an item indicating the integrated node is deleted. If the number of items of the parent node is decreased, the process is repeated. If a searching process is started, the searching result is obtained by the above (S602) and (S605) stages.

Abstract translation: 目的：提供一种考虑存储器层次结构来压缩，搜索和插入新项目的方法，通过使用一个节点中的一个指针来增加多重搜索树的速度，从而识别（密钥的数量x密钥的大小+ 指针大小）与高速缓存行的大小。 构成：如果开始新的项目处理（S601），则搜索新项目附加的位置（S602），将新的项目附加到其节点。 此外，如果节点已满，则将中值附加到父节点，并将子节点分成并插入到两个连续的存储器中（S603）。 要添加到父节点中的进程用添加到当前节点的方法来标识。 如果特定节点删除处理开始（S604），则搜索要删除的位置（S605），从相应的节点删除对应的项目（S606）。 作为删除的结果，如果相应节点的项目数量减少到小于其一半的节点，则将节点集成到相邻节点，并且具有两个节点的子节点的两个连续存储器被集成为一个连续的存储器。 如果由删除引起的两个相邻节点被集成，则表示集成节点的项目被删除。 如果父节点的数量减少，则重复该过程。 如果搜索过程开始，则通过上述（S602）和（S605）阶段获得搜索结果。

公开(公告)号：KR1019960024965A

公开(公告)日：1996-07-20

申请号：KR1019940036143

申请日：1994-12-23

Applicant: 한국전자통신연구원 ,  주식회사 케이티

Inventor： 도한철 ,  김재근

IPC: G06F11/30

Abstract: 본 발명은 신호보드로부터 실, 탈장 인식값의 변화를 감지하는 실, 탈장 인식모듈(1)과, 상기 실, 탈장 인식모듈(1)로부터 최초 인식전의 값을 입력받아 저장하는 상태저장모듈(2)과, 상기 저장한 값과 현재의 값을 비교하여 실질적인 실, 탈장에 의한 변화인지 잡음에 의한 일시적인 변화인지를 구별하게 하는 2차 인식모듈(3)과, 상기 변화이후 일정시간 경과동안 실, 탈장 인식모듈(1)을 마스킹하여 다른 변화를 인식하지 못하게 하고, 시간경과후 발생된 인터럽트를 플립플롭에 래치시키도록 클럭을 만들어주는 시간지연모듈(4)을 구비하는 것을 특징으로 하여, 시스템에서 임의로 제어대상 보드가 실, 탈장될 경우, 이를 감지하여 인터럽트를 발생하므로서 프로세서에 의한 조치가 즉시 이루어지도록 하는 인터럽트에 의한 보드실탈장 감지회로에 관한 것 이다.

公开(公告)号：KR100328129B1

公开(公告)日：2002-03-12

申请号：KR1019990062376

申请日：1999-12-27

Applicant: 한국전자통신연구원

Inventor： 안석순 ,  도한철 ,  이형호

IPC: G06F17/30

Abstract: 본발명은다중탐색트리에서한 노드에서사용하는포인터의개수를 1개만사용하도록하여 (키의개수 × 키의크기 + 포인터크기)를캐시라인크기와일치시켜다중탐색트리를고속화하고, 키의크기와포인터의크기가비슷한네트워크어드레스탐색에서분기수를 2배가까이늘려탐색을고속화하여포워딩엔진의속도를높이는 B-tree 계열에기반한메모리계층(Memory Hierarchy) 구조를고려한압축, 탐색및 새로운항목삽입방법을제공하는데그 목적이있다. 본발명에따르면, B-tree 계열에기반한메모리계층(Memory Hierarchy) 구조를고려한압축및 탐색방법에있어서, 동일한부모노드(Parent Node)를가진자식노드(Child Node)들을연속된메모리영역에배치하여한 노드당한 개의포인터(Pointer)만사용하여자식노드들을가리키는것을특징으로하는메모리계층구조를고려한압축및 탐색방법이제공된다.

公开(公告)号：KR100317126B1

公开(公告)日：2001-12-24

申请号：KR1019990062449

申请日：1999-12-27

Applicant: 한국전자통신연구원

Inventor： 도한철 ,  이형호 ,  안석순 ,  김기민

IPC: H04L12/28

Abstract: 본발명은네트워크기술에서이더넷기반의패킷포워딩에관한것으로특히, 기가비트속도의트래픽을만족하는빠른 3계층포워딩을구현하기위해 3계층포워딩엔진을기가비트이더넷매체제어기(Media Access Controller) 내부에실장함으로써지연및 처리시간을최대한없애고이중경로(2-way path) 방식의효율적인 3계층포워딩엔진구조를사용하여메시지트래픽의분산처리를통한기가비트속도의밴드폭을보장하도록하는이중경로방식의 3계층포워딩엔진을갖는기가비트이더넷구조를제공한다. 또한 MAC 내부에기가비트속도의 MAC 프로토콜과 3계층포워딩을구현함으로써기존의분리된 MAC과포워딩엔진장치가갖고있는시간지연요인(Lateny)을없애고기가비트대역폭을보장하는속도로전송이이루어지게된다.