公开(公告)号：KR1020120057679A

公开(公告)日：2012-06-07

申请号：KR1020100075412

申请日：2010-08-05

Applicant: 한국전자통신연구원

Inventor： 심재우

IPC: G06F17/21 ,  G06F17/26

CPC classification number: G06F17/30985

Abstract: PURPOSE: A character pattern storing apparatus through divided TCAM is provided to increase spatial/temporal efficiency of a memory by storing patterns according to each component size. CONSTITUTION: A distributing unit(100) distributes character patterns which is inputted according to an operating mode according to components of corresponding character patterns. A TCAM(200) is distributed into areas where character patterns are distributed. The distributed areas have different priorities. A selecting unit(300) selects a pattern which is stored in one distributed area.

Abstract translation: 目的：通过分割的TCAM提供字符图形存储装置，以通过根据每个组件尺寸存储图案来增加存储器的空间/时间效率。 构成：分配单元（100）根据操作模式分配根据相应字符模式的分量输入的字符图案。 TCAM（200）被分配到分布有字符模式的区域。 分布区域有不同的优先事项。 选择单元（300）选择存储在一个分布区域中的模式。

公开(公告)号：KR1020120072125A

公开(公告)日：2012-07-03

申请号：KR1020100133934

申请日：2010-12-23

Applicant: 한국전자통신연구원

Inventor： 신치훈 ,  김성남 ,  오명훈 ,  김성운 ,  심재우

IPC: H03K5/13 ,  H03K19/173

CPC classification number: G06F17/5027 ,  G06F17/5059

Abstract: PURPOSE: A delay circuit and an asynchronous circuit simulation apparatus and method in a FPGA(Field Programmable Gate Array) using the same are provided to form a delay circuit by using a look up table within the FPGA. CONSTITUTION: The asynchronous circuit simulation apparatus in a FPGA(Field Programmable Gate Array)(10) includes a control part(300), a function execution part(200), and a delay circuit(100). A plurality of function execution parts is formed according to a plurality of unit functions included in an asynchronous circuit to be simulated. A plurality of delay circuits corresponding to the function execution parts is formed in a proportional to the number of the function execution parts. The control part transmits an input signal requesting a delayed input signal and unit performance function to the delay circuit and the function execution part.

Abstract translation: 目的：提供使用FPGA的FPGA（现场可编程门阵列）中的延迟电路和异步电路仿真装置和方法，以便通过使用FPGA内的查找表形成延迟电路。 构成：FPGA（现场可编程门阵列）（10）中的异步电路仿真装置包括控制部分（300），功能执行部分（200）和延迟电路（100）。 根据包含在待仿真的异步电路中的多个单元功能，形成多个功能执行部。 与功能执行部分的数量成比例地形成与功能执行部分对应的多个延迟电路。 控制部将延迟输入信号和单位性能函数的输入信号发送到延迟电路和功能执行部。