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公开(公告)号：KR101502759B1
公开(公告)日：2015-03-24
申请号：KR1020120032855
申请日：2012-03-30
Applicant: 한국전자통신연구원
IPC: H04L25/02 , H03K19/0175
CPC classification number: G06F17/5059
Abstract: 데이터 송신 장치, 데이터 수신 장치 및 데이터 전송 방법이 개시된다. 본 발명에 따른 데이터 송신 장치, 데이터 수신 장치 및 데이터 전송 방법은 지연 소자를 통한 상태 저장 대신 유한 상태 머신(Finite State Machine; FSM) 로직을 이용함으로써, 요구 신호 및 데이터 신호와 관련한 시간에 대한 가정이 필요없고, 디코더에 클록 신호를 만들어주는 부가 로직이 필요 없어서, 디코더의 회로 구조를 단순화할 수 있다.
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公开(公告)号：KR1020130134618A
公开(公告)日：2013-12-10
申请号：KR1020120058247
申请日：2012-05-31
Applicant: 한국전자통신연구원
IPC: H03K19/173 , G06F17/50
CPC classification number: G06F17/5072 , G06F17/505 , G06F2217/78
Abstract: The present invention relates to an apparatus for reducing peak power using asynchronous circuit design technology comprising: a combinational circuit unit for dividing a combinational circuit into multiple partial circuits based on the depth of input and output; and an asynchronous control circuit unit for asynchronously setting switch operations of the partial circuits according to a temporal relation and controlling the combinational circuit so that the switch operations do not occur in different partial circuits in case the switch operation occurs in one partial circuit. [Reference numerals] (220) Asynchronous control circuit unit;(230,DD,EE,FF) Barrier gate circuit unit;(240,AA,BB,CC) Delay device unit;(250) Proximity circuit unit
Abstract translation: 本发明涉及一种使用异步电路设计技术降低峰值功率的装置，包括：组合电路单元，用于基于输入和输出的深度将组合电路分为多个部分电路; 以及异步控制电路单元，用于根据时间关系异步地设置部分电路的切换操作，并且控制组合电路，使得在一个部分电路中发生开关操作的情况下，在不同的部分电路中不发生开关操作。 （220）异步控制电路单元;（230，DD，EE，FF）阻挡门电路单元;（240，AA，BB，CC）延迟设备单元;（250）接近电路单元
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公开(公告)号：KR1020120072125A
公开(公告)日：2012-07-03
申请号：KR1020100133934
申请日：2010-12-23
Applicant: 한국전자통신연구원
IPC: H03K5/13 , H03K19/173
CPC classification number: G06F17/5027 , G06F17/5059
Abstract: PURPOSE: A delay circuit and an asynchronous circuit simulation apparatus and method in a FPGA(Field Programmable Gate Array) using the same are provided to form a delay circuit by using a look up table within the FPGA. CONSTITUTION: The asynchronous circuit simulation apparatus in a FPGA(Field Programmable Gate Array)(10) includes a control part(300), a function execution part(200), and a delay circuit(100). A plurality of function execution parts is formed according to a plurality of unit functions included in an asynchronous circuit to be simulated. A plurality of delay circuits corresponding to the function execution parts is formed in a proportional to the number of the function execution parts. The control part transmits an input signal requesting a delayed input signal and unit performance function to the delay circuit and the function execution part.
Abstract translation: 目的：提供使用FPGA的FPGA（现场可编程门阵列）中的延迟电路和异步电路仿真装置和方法，以便通过使用FPGA内的查找表形成延迟电路。 构成：FPGA（现场可编程门阵列）（10）中的异步电路仿真装置包括控制部分（300），功能执行部分（200）和延迟电路（100）。 根据包含在待仿真的异步电路中的多个单元功能，形成多个功能执行部。 与功能执行部分的数量成比例地形成与功能执行部分对应的多个延迟电路。 控制部将延迟输入信号和单位性能函数的输入信号发送到延迟电路和功能执行部。
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公开(公告)号：KR1020100064440A
公开(公告)日：2010-06-15
申请号：KR1020080122874
申请日：2008-12-05
Applicant: 한국전자통신연구원
CPC classification number: G11C16/06 , B82Y10/00 , G11C11/16 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0014 , G11C13/025 , G11C16/10 , G11C16/26
Abstract: PURPOSE: Sequential circuits, integrated circuits and a method for driving the same are provided to rapidly block and reapply power by replacing all memory devices with non-volatile memory devices. CONSTITUTION: A combinational logic generates a new state variable using a stored state variable during a driving operation. A non-volatile memory device(100) provides a state variable as a combinational logic. The non-volatile memory device stores the new state variable. A read circuit(30) reads the state variable which is stored in the non-volatile memory during the driving operation and provides the stored state variable as the combinational logic. A wire circuit(10) writes a new state variable in the non-volatile memory.
Abstract translation: 目的：提供顺序电路，集成电路及其驱动方法，以通过用非易失性存储器件替换所有存储器件来快速阻断和重新供电。 组合：组合逻辑在驾驶操作期间使用存储的状态变量生成新的状态变量。 非易失性存储器件（100）提供状态变量作为组合逻辑。 非易失性存储器件存储新的状态变量。 读取电路（30）读取在驱动操作期间存储在非易失性存储器中的状态变量，并将存储的状态变量提供为组合逻辑。 有线电路（10）将新的状态变量写入非易失性存储器。
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公开(公告)号：KR100934215B1
公开(公告)日：2009-12-29
申请号：KR1020070109206
申请日：2007-10-29
Applicant: 한국전자통신연구원
CPC classification number: G06F9/30003
Abstract: Provided are a microprocessor based on event-processing instruction set and an event-processing method using the same. The microprocessor includes an event register controlling an event according to an event-processing instruction set provided in an instruction set architecture (ISA) and an event controller transmitting externally generated events into the microprocessor. Therefore, the microprocessor may be useful to reduce its unnecessary power consumption by suspending the execution of its program when an instruction decoded to execute the program is an event-processing instruction, and also to cut off its unnecessary power consumption that is caused for an interrupt delay period since the program of the microprocessor may be executed again by immediately re-running the microprocessor with the operation of the event register and the event controller when external events are generated.
Abstract translation: 提供了一种基于事件处理指令集的微处理器和使用该微处理器的事件处理方法。 微处理器包括事件寄存器，事件寄存器根据指令集体系结构（ISA）中提供的事件处理指令集和事件控制器将外部产生的事件传送到微处理器中来控制事件。 因此，当被解码为执行程序的指令是事件处理指令时，微处理器可以通过暂停其程序的执行来减少其不必要的功耗，并且还切断其由于中断而导致的不必要的功耗 由于微处理器的程序可以通过在外部事件产生时通过事件寄存器和事件控制器的操作立即重新运行微处理器而被再次执行。
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Patent Agency Ranking
公开(公告)号：KR100452325B1
公开(公告)日：2004-10-12
申请号：KR1020020082895
申请日：2002-12-23
Applicant: 한국전자통신연구원
IPC: G06F13/00
Abstract: PURPOSE: An AMBA(Advanced Micro-controller Bus Architecture) bus based multiprocessor system to assign a processor number and be sequentially booted is provided to easily realize a shared-bus based multiprocessor system and enable the installation of a multiprocessor OS(Operating System) later on by assigning a processor ID and sequentially booting the multiprocessor. CONSTITUTION: The bus provides an address/control signal line, a read data signal line, and a write data signal line connecting the masters(210-1¯210-3) with other resources. A bus arbiter(230) generates an internal bus request signal depending on a bus enable signal by receiving the bus request signal from the master, controls a bus use permission of each bus master depending on the internal bus request signal, and outputs a bus user number of the master receiving the bus use permission. A multiprocessor supporting slave(280) provides the bus enable signal to the bus arbiter and receives/stores the bus user number from the bus arbiter.
Abstract translation: 目的：提供AMBA（高级微控制器总线架构）总线多处理器系统来分配处理器编号并被顺序引导，以便轻松实现基于共享总线的多处理器系统，并能够在稍后安装多处理器OS（操作系统） 通过分配处理器ID并依次引导多处理器。 构成：总线提供地址/控制信号线，读数据信号线和写数据信号线，将主设备（210-1和210-3）与其他资源连接起来。 总线仲裁器（230）根据总线使能信号通过接收来自主设备的总线请求信号产生内部总线请求信号，根据内部总线请求信号控制每个总线主设备的总线使用许可，并且输出总线用户 接收总线使用权限的主设备号码。 支持从设备（280）的多处理器向总线仲裁器提供总线使能信号，并从总线仲裁器接收/存储总线使用者号码。
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公开(公告)号：KR1020040056293A
公开(公告)日：2004-06-30
申请号：KR1020020082895
申请日：2002-12-23
Applicant: 한국전자통신연구원
IPC: G06F13/00
Abstract: PURPOSE: An AMBA(Advanced Micro-controller Bus Architecture) bus based multiprocessor system to assign a processor number and be sequentially booted is provided to easily realize a shared-bus based multiprocessor system and enable the installation of a multiprocessor OS(Operating System) later on by assigning a processor ID and sequentially booting the multiprocessor. CONSTITUTION: The bus provides an address/control signal line, a read data signal line, and a write data signal line connecting the masters(210-1¯210-3) with other resources. A bus arbiter(230) generates an internal bus request signal depending on a bus enable signal by receiving the bus request signal from the master, controls a bus use permission of each bus master depending on the internal bus request signal, and outputs a bus user number of the master receiving the bus use permission. A multiprocessor supporting slave(280) provides the bus enable signal to the bus arbiter and receives/stores the bus user number from the bus arbiter.
Abstract translation: 目的：提供用于分配处理器号并被顺序启动的基于总线架构的AMBA（高级微控制器总线体系结构）总线系统，以便轻松实现基于共享总线的多处理器系统，并且可以稍后安装多处理器OS（操作系统） 通过分配处理器ID并顺序引导多处理器。 构成：总线提供地址/控制信号线，读数据信号线和连接主机（210-1〜210-3）与其他资源的写数据信号线。 总线仲裁器（230）通过从主机接收总线请求信号，根据总线使能信号产生内部总线请求信号，根据内部总线请求信号控制每个总线主机的总线使用许可，并输出总线用户 接收总线使用许可的主机号码。 多处理器支持从站（280）向总线仲裁器提供总线使能信号，并从总线仲裁器接收/存储总线用户号码。
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公开(公告)号：KR101173942B1
公开(公告)日：2012-08-14
申请号：KR1020080119279
申请日：2008-11-28
Applicant: 한국전자통신연구원
IPC: H04L7/00
CPC classification number: H04L25/4923
Abstract: 지연 무관 데이터 전송 방식을 이용하여 데이터 전송하는 데이터 전송 장치 및 데이터 전송 방법이 제공된다. 이 데이터 전송 장치 및 데이터 전송 방법은 2-위상 핸드셰이크 프로토콜을 지원하는 지연 무관 데이터 전송방식을 이용하고, 데이터의 전송시 3진 인코딩 방식에 의해 스페이 상태가 없는 3가지 논리 상태로 상기 데이터가 인코딩된다. 이러한 상기 데이터 전송 장치 및 데이터 전송 방법에 의하면, 도선의 길이에 무관하게 데이터가 안전하게 수신측으로 전송되고, 데이터 전송률 측면에서 기존의 4-위상 지연 데이터 전송 방식에 비해 보다 향상된 성능을 제공한다.
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公开(公告)号：KR1020120042015A
公开(公告)日：2012-05-03
申请号：KR1020100103472
申请日：2010-10-22
Applicant: 한국전자통신연구원
CPC classification number: G06F9/3871 , G06F9/3869
Abstract: PURPOSE: An asynchronous pipeline system, a stage, and a data transfer method are provided to reduce power consumption necessary for data transfer by selectively receiving necessary on-demand data. CONSTITUTION: An always input block is a transfer path of control data from a previous stage. An on-demand input block(140) receives one on-demand data from the previous stage. If a handshake protocol request signal is transferred from the previous stage, a control block(110) enables the input block. A stage logic(120) receives control data through the input block according to the enable of the control block and confirms the on-demand data.
Abstract translation: 目的：提供异步流水线系统，阶段和数据传输方法，通过选择性地接收必要的按需数据来减少数据传输所需的功耗。 总则：总是输入块是来自前一级的控制数据的传输路径。 按需输入块（140）从前一级接收一个按需数据。 如果从前一级传送握手协议请求信号，则控制块（110）启用输入块。 阶段逻辑（120）根据控制块的使能通过输入块接收控制数据，并确认按需数据。
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公开(公告)号：KR1020100062147A
公开(公告)日：2010-06-10
申请号：KR1020080120596
申请日：2008-12-01
Applicant: 한국전자통신연구원
CPC classification number: H03K19/0016 , H03K17/94 , H03K19/0175
Abstract: PURPOSE: A power gating circuit and a semiconductor device including the same are provided to maximize efficiency without a software algorithm cost by implementing a power gating circuit with a self-control method. CONSTITUTION: A logic block(300,301) receives a power voltage and processes an input signal. A controller(100) provides a request signal of a first level to apply a power voltage to a logic block and provides the request signal of a second level if a response signal for the request signal is received. A power gating circuit(200,201) receives the request signal of the first level and applies the power voltage to the logic block. The power gating circuit provides the response signal to the controller if a process completion signal is outputted, and blocks the power voltage by receiving the request signal of the second level.
Abstract translation: 目的：提供电源门控电路和包括该电源门控电路的半导体器件，以通过使用自控方法实现电源门控电路来最大限度地提高效率而无需软件算法成本。 构成：逻辑块（300,301）接收电源电压并处理输入信号。 如果接收到请求信号的响应信号，则控制器（100）提供第一电平的请求信号以将电源电压施加到逻辑块并且提供第二电平的请求信号。 电源门控电路（200,201）接收第一电平的请求信号，并将电源电压施加到逻辑块。 如果输出处理完成信号，则电源门控电路向控制器提供响应信号，并通过接收第二电平的请求信号来阻断电源电压。
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