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Patent Agency Ranking
公开(公告)号：KR1019920007170B1
公开(公告)日：1992-08-27
申请号：KR1019890019307
申请日：1989-12-22
Applicant: 한국전자통신연구원
IPC: G06F13/32
Abstract: The interrupt bus is for communicating asynchronous signals between modules of multiprocessor system. The unit includes an inerrupt requester (4) for sending interrupt transmission request signal of system module to a corresponding interrupt processor, interrupt processors (5,6) for sending interrupt signal to the corresponding module, an interrupt signal to the corresponding module, an interrupt arbiter (7) for arbitrating the usage of the interrupt bus, a first and a second interrupt requester register (8,10) for storing data of the interrupt requester, a first and a second interrupt processor register, and adaptors (12,13) for forming signal line among the interrupt requestor (4), the interrup processors (5,6) and the interrupt bus (3).
Abstract translation: 中断总线用于在多处理器系统的模块之间传送异步信号。 该单元包括用于向对应的中断处理器发送系统模块的中断发送请求信号的中断请求器（4），用于向相应模块发送中断信号的中断处理器（5,6），对应模块的中断信号，中断 用于仲裁中断总线的使用的仲裁器（7），用于存储中断请求者的数据的第一和第二中断请求者寄存器（8,10），第一和第二中断处理器寄存器以及适配器（12,13） 用于在中断请求器（4），中断处理器（5,6）和中断总线（3）之间形成信号线。
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公开(公告)号：KR1019920007945B1
公开(公告)日：1992-09-19
申请号：KR1019890019676
申请日：1989-12-27
Applicant: 한국전자통신연구원
IPC: G06F12/00
Abstract: The slot address designating method is to designating positions for slots of each system bus exclusively so that the processor boards inserted to the slots detects the position to which the boards are inserted. The position data for each processor board are assigned to signal pins of system bus (3) and the address designation or the interleaving sequence control is executed with priority.
Abstract translation: 插槽地址指定方法是专门为每个系统总线的时隙指定位置，以便插入插槽的处理器板检测插入板的位置。 每个处理器板的位置数据被分配给系统总线（3）的信号引脚，优先执行地址指定或交织序列控制。
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