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公开(公告)号：KR1019900007098B1
公开(公告)日：1990-09-28
申请号：KR1019870011425
申请日：1987-10-14
Applicant: 한국전자통신연구원
Inventor： 조삼현
IPC: G06F13/14
Abstract: The art bus (2) for processing various signal of the process control system with personal computer equips a number of I/O cards (1) at connectors (3a-h) which are connected to a master card (4) in parallel through a master connector (3m). A process control board (6) inserted in an expansion slot of the personal computer is connected to the master card through a connector cable. The I/O card processing the data, address, control, and interrupt signals may be expanded to 8 in maximum.
Abstract translation: 用于处理具有个人计算机的过程控制系统的各种信号的艺术总线（2）在连接器（3a-h）处配备多个I / O卡（1），所述连接器（3a-h）通过 主连接器（3m）。 插入个人计算机的扩展槽中的过程控制板（6）通过连接器电缆连接到主卡。 处理数据，地址，控制和中断信号的I / O卡最多可扩展到8个。
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Patent Agency Ranking
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公开(公告)号：KR1019900007126B1
公开(公告)日：1990-09-29
申请号：KR1019870011568
申请日：1987-10-19
Applicant: 한국전자통신연구원
Inventor： 조삼현
IPC: G06F13/14
Abstract: The circuit for processing I/O data in a process control system using a personal computer comprises decoders (A,B) decoding input address (A0-1), selection (CS), write control (WR), and read control (RD) signals; an input buffer (C) inputting 2 digital signals by an input control signal of the decoder (B); a bidirectional bus signal transmitter (D) controlling the data dirction; and an output latch (E) outputting the 32 digital signal by output control signal of the decoder (A) so that 32 I/O signals are processed.
Abstract translation: 在使用个人计算机的处理控制系统中处理I / O数据的电路包括解码器（A，B）解码输入地址（A0-1），选择（CS），写入控制（WR）和读取控制（RD） 信号; 通过解码器（B）的输入控制信号输入2个数字信号的输入缓冲器（C）; 双向总线信号发射器（D），用于控制数据反向; 以及通过解码器（A）的输出控制信号输出32数字信号的输出锁存器（E），从而处理32个I / O信号。
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公开(公告)号：KR1019900005799B1
公开(公告)日：1990-08-11
申请号：KR1019870011570
申请日：1987-10-19
Applicant: 한국전자통신연구원
Inventor： 조삼현
IPC: G06F13/22
Abstract: The I/O data scanning apparatus comprises a microprocessor (1) for deciding the data processing and the operation sequence for I/O scanning, a control logic (2) for deciding the on/off state and direction of data signal in bus buffers (6,7,8) and a buffer (9), an internal memory (3) for performing program of microprocessor and storing data, a first bus buffer (6) for buffering the transmitted/ received data from PC, a FIFO memory (4) for storing temporarily the I/O data of the first buffer, a FIFO address control logic (5) for controlling address of the FIFO memory, and a third bus buffer for buffering the I/O data between FIFO memory and I/O device.
Abstract translation: I / O数据扫描装置包括用于决定数据处理的微处理器（1）和用于I / O扫描的操作顺序，用于决定总线缓冲器中的数据信号的开/关状态和方向的控制逻辑（2） 6,7,8）和缓冲器（9），用于执行微处理器程序并存储数据的内部存储器（3），用于从PC缓冲发送/接收数据的第一总线缓冲器（6），FIFO存储器 ），用于临时存储第一缓冲器的I / O数据，用于控制FIFO存储器的地址的FIFO地址控制逻辑（5）和用于缓冲FIFO存储器和I / O设备之间的I / O数据的第三总线缓冲器 。
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公开(公告)号：KR1019890002433B1
公开(公告)日：1989-07-03
申请号：KR1019860006095
申请日：1986-07-25
Applicant: 한국전자통신연구원
Abstract: The apparatus comprises a CPU (Intel 8085), two input-output processors (Intel 8255 (8,9)) a tranceiver (2) (Intel 74245) for connecting memory and displaying the abnormal and emergency situations, a Darlington circuit for the pressure and water level controls, an inverter, and a switch for feul selections.
Abstract translation: 该装置包括用于连接存储器并显示异常和紧急情况的CPU（Intel 8085），两个输入输出处理器（Intel 8255（8,9））收发器（2）（Intel 74245），用于压力的达林顿电路 和水位控制，逆变器和用于选择的开关。
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