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公开(公告)号：KR1020000018592A
公开(公告)日：2000-04-06
申请号：KR1019980036241
申请日：1998-09-03
Applicant: 한민구
IPC: H01L29/786
Abstract: PURPOSE: A manufacturing method of a TFT(Thin Film Transistor) is provided to improve a channel structure for optimizing a hydrogenating effect. CONSTITUTION: A manufacturing method of a TFT(Thin Film Transistor) comprises the steps of: forming a first insulation layer on a substrate; forming a first conductive layer on the first insulation layer; forming a multi channel having a plurality of channels for securing an inflow path of a hydrogen radical between the source/drain regions of an activation region in a succeeding hydrogenating process simultaneously with defining the activation region by performing a photo lithography and an etching precesses on the first conductive layer; forming a second insulation layer and a second conductive layer on the entire surface; forming a gate electrode having a plurality of grooves in the channel direction for securing an inflow path of a hydrogen radical in a succeeding hydrogenating process simultaneously with patterning the second insulation layer and the second conductive layer; forming injecting impurity ions into the gate electrode and source/drain regions by using the gate electrode as self-aligned ion-implanting mask and forming a passivation layer; performing a hydrogenating process on the entire surface; and connecting the gate electrode and the source/drain regions with a metal line for applying the external voltage to the gate electrode and the source/drain regions.
Abstract translation: 目的：提供TFT（薄膜晶体管）的制造方法，以改善用于优化氢化效果的通道结构。 构成：TFT（薄膜晶体管）的制造方法包括以下步骤：在基板上形成第一绝缘层; 在所述第一绝缘层上形成第一导电层; 形成具有多个通道的多通道，用于在后续氢化过程中在激活区域的源极/漏极区域之间固定氢自由基的流入路径，同时通过执行光刻和蚀刻进入限定激活区域 第一导电层; 在整个表面上形成第二绝缘层和第二导电层; 在所述沟道方向上形成具有多个槽的栅电极，用于在对所述第二绝缘层和所述第二导电层进行构图的同时，在随后的氢化工艺中固定氢自由基的流入路径; 通过使用栅电极作为自对准离子注入掩模形成注入杂质离子到栅电极和源/漏区，并形成钝化层; 在整个表面上进行氢化处理; 以及用栅极电极和源极/漏极区域施加外部电压的金属线连接栅极电极和源极/漏极区域。
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公开(公告)号：KR100268063B1
公开(公告)日：2000-10-16
申请号：KR1019960053781
申请日：1996-11-13
IPC: H01L29/786
Abstract: PURPOSE: A thin film transistor having an area for suppressing a leakage current into a channel is provided to effectively reduce a leakage current in an off operation without an additional process, present the characteristic of an offset gate structure in an off state, operate as a non-offset structure in an on state, reduce the leakage current in larger numbers than that of a transistor composed of an offset structure without reducing the amount of an on current in an on operation than the amount of an on current of a transistor composed of a non-offset structure and operatively delete an offset area so as to have an enough gate driving capacity in a turn-on operation and operatively form the offset area so as to cut off a leakage current in a turn-off operation only. CONSTITUTION: The thin film transistor includes a channel area(12P), a gate insulating film(14), source and drain areas(12P(S),12P(D)) and a transparent gate area. The channel area has an off-set area(12a,12b) in the vicinity of both ends. The gate insulating film is formed on the channel area. The source area is formed to the first adjacent portion on the boundary the off-set area of the channel area. The drain area is formed to the second adjacent portion on the boundary the off-set area of the channel area. The transparent gate area is formed to the same length as the gate insulating film on the upper of the gate insulating and has an opaque film in the vicinity of both ends as a length being vertically opposite to the off-set area.
Abstract translation: 目的：提供一种薄膜晶体管，其具有用于抑制流入沟道的漏电流的区域，以便在没有附加处理的情况下有效地减少关断操作中的漏电流，将偏移栅极结构的特性呈现在断开状态，作为 非偏移结构处于导通状态，从而减小漏极电流大于由偏移结构组成的晶体管的漏电流，而不会减少导通电流导通电流的量，而不是由晶体管的导通电流量 非偏移结构，并且操作地删除偏移区域，以便在接通操作中具有足够的栅极驱动能力并且可操作地形成偏移区域，以便仅在关断操作中切断泄漏电流。 构成：薄膜晶体管包括沟道区（12P），栅极绝缘膜（14），源区和漏极区（12P（S），12P（D））和透明栅区。 通道区域在两端附近具有偏移区域（12a，12b）。 栅极绝缘膜形成在沟道区域上。 源极区域形成在边界上的第一相邻部分，该通道区域的偏移区域。 漏极区域形成在边界上的第二相邻部分，该通道区域的偏移区域。 透明栅极区域形成为与栅极绝缘体的上部的栅极绝缘膜相同的长度，并且在两端附近具有与偏移区域垂直相反的长度的不透明膜。
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公开(公告)号：KR100278053B1
公开(公告)日：2001-02-01
申请号：KR1019980036241
申请日：1998-09-03
Applicant: 한민구
IPC: H01L29/786
Abstract: 본 발명은 박막 트랜지스터 및 그 제조 방법에 관한 것이다. 본 발명에 따르면, 박막 트랜지스터의 특성을 향상시키는 수소화 효과를 보다 증대시키기 위해, 박막 트랜지스터의 채널 및 게이트 전극에 사진 및 식각 공정을 실시하여 다수개의 채널을 가지는 멀티 채널 구조를 형성하고, 게이트 전극에도 채널 방향으로의 홈들을 형성한다. 그 결과 수소 유입면적이 증가되어 수소 래디칼들의 유입경로가 확보되고, 이에 따라 채널 내로의 수소 유입량이 증가되어 수소화 효과가 증대됨으로써, 박막 트랜지스터의 드레인 전류 및 문턱 전압등의 특성이 향상된다.
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