公开(公告)号：EP1256132A1

公开(公告)日：2002-11-13

申请号：EP01905860.1

申请日：2001-01-30

Applicant: 3D Plus

Inventor： VAL, ChristianThomson-CSF Propriété Intell.

IPC: H01L25/10 ,  H01L21/98

CPC classification number: H01L25/50 ,  H01L25/105 ,  H01L2224/48091 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2225/1029 ,  H01L2225/1064 ,  H01L2924/0102 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: The invention concerns a three-dimensional interconnection method and an electronic device obtained by said method. The inventive method for increasing compactness of integrated circuit modules consists in stacking and bonding (100) housings containing a chip connected to output pins with connecting conductors inside each housing; cutting (101) through the housings in the proximity of the chips to form a block, the conductors being flush with the surfaces of the block; and producing (102) the connections on the surfaces of the block by metallizing (1021) then engraving (1022) the outlines of the connections. The method is also useful for adapting replacement housings of obsolete circuits.

Abstract translation: 在通过该方法获得的电子装置在三维空间中，并互连的方法。 为了增加集成电路模块，所述方法堆栈和包含由每个封装内部连接导体电连接到输出引线的芯片粘接键封装紧凑，通过芯片附近的包切口以形成块，导体是与的面齐平 块，并且使得所述块的通过金属喷涂的面，然后蚀刻所述连接的轮廓的连接。 因此，该方法适用于包在更换过时的电路的匹配。