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公开(公告)号:US11343943B1
公开(公告)日:2022-05-24
申请号:US17101621
申请日:2020-11-23
Applicant: ABB Schweiz AG
Inventor: Giovanni Salvatore , Slavo Kicin , Fabian Mohn
Abstract: Systems, methods, techniques and apparatuses of power switches are disclosed. One exemplary embodiment is a power switch comprising an outer housing; a power electronics board disposed within the housing and including a semiconductor switch structured to selectively conduct a current between a first power terminal and a second power terminal; a first heat sink coupled to the power electronics board; a plurality of thermally conductive connectors; a second heat sink coupled to the plurality of thermally conductive connectors, a control electronics board structured to control the semiconductor switch, the control electronics board being located within an enclosure formed of the second heat sink, the plurality of thermally conductive connectors, and the power electronics board.
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公开(公告)号:US10950516B2
公开(公告)日:2021-03-16
申请号:US16673201
申请日:2019-11-04
Applicant: ABB Schweiz AG , Audi AG
Inventor: Fabian Mohn
IPC: H01L23/31 , H01L21/48 , H01L21/56 , H01L23/367 , H01L23/498 , H01L25/16 , H01L23/00
Abstract: A power semiconductor module includes a substrate with a metallization layer; at least one power semiconductor chip bonded to the substrate; and a mold encapsulation partially encapsulating the semiconductor chip and the substrate; the mold encapsulation includes at least one window exposing a terminal area of the metallization layer; and a border part of the mold encapsulation between the window and a border of the substrate has a height over the substrate smaller than a maximal height of a central part of the mold encapsulation.
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公开(公告)号:US20190273040A1
公开(公告)日:2019-09-05
申请号:US16419668
申请日:2019-05-22
Applicant: ABB Schweiz AG , Audi AG
Inventor: Fabian Mohn , Chunlei Liu , Jürgen Schuderer
IPC: H01L23/498 , H01L21/48 , H01L21/56 , H01L23/31
Abstract: A semi-manufactured power semiconductor module includes a substrate for bonding at least one power semiconductor chip; a first leadframe bonded to the substrate and providing power terminals; and a second leadframe bonded to the substrate and providing auxiliary terminals; wherein the first leadframe and/or the second leadframe include an interlocking element adapted for aligning the first leadframe and the second leadframe with respect to each other and/or with respect to a mold for molding an encapsulation around the substrate, the first leadframe and the second leadframe.
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公开(公告)号:US20180040538A1
公开(公告)日:2018-02-08
申请号:US15783193
申请日:2017-10-13
Applicant: ABB Schweiz AG
Inventor: Juergen Schuderer , Fabian Mohn , Didier Cottet , Felix Traub , Daniel Kearney
IPC: H01L23/473 , H01L23/498 , H01L23/31 , H01L29/16 , H01L25/07 , H01L23/00
CPC classification number: H01L23/473 , H01L23/3142 , H01L23/49844 , H01L24/48 , H01L24/49 , H01L25/071 , H01L29/1608 , H01L2224/33 , H01L2224/48091 , H01L2924/00014
Abstract: A power electronics module comprises a first liquid cooler comprising a cooling channel for receiving a cooling liquid, wherein the first liquid cooler comprises a metal body providing a first terminal of the power electronics module; a second liquid cooler comprising a cooling channel for receiving a cooling liquid, wherein the second liquid cooler comprises a metal body providing a second terminal of the power electronics module; a plurality of semiconductor chips arranged between the first liquid cooler and the second liquid cooler, such that a first electrode of each semiconductor chip is bonded to the first liquid cooler, such that the first electrode is in electrical contact with the first liquid cooler, and an opposite second electrode of each semiconductor chip is in electrical contact with the second liquid cooler; and an insulating encapsulation, formed by molding the first liquid cooler, the second liquid cooler and the plurality of semiconductor chips into an insulation material, such that the first liquid cooler, the second liquid cooler and the plurality of semiconductor chips are at least partially embedded onto the insulation material.
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公开(公告)号:US10283436B2
公开(公告)日:2019-05-07
申请号:US15783193
申请日:2017-10-13
Applicant: ABB Schweiz AG
Inventor: Juergen Schuderer , Fabian Mohn , Didier Cottet , Felix Traub , Daniel Kearney
IPC: H01L23/473 , H01L25/07 , H01L23/31 , H01L23/498 , H01L23/00 , H01L29/16
Abstract: A power electronics module comprises a first liquid cooler comprising a cooling channel for receiving a cooling liquid, wherein the first liquid cooler comprises a metal body providing a first terminal of the power electronics module; a second liquid cooler comprising a cooling channel for receiving a cooling liquid, wherein the second liquid cooler comprises a metal body providing a second terminal of the power electronics module; a plurality of semiconductor chips arranged between the first liquid cooler and the second liquid cooler, such that a first electrode of each semiconductor chip is bonded to the first liquid cooler, such that the first electrode is in electrical contact with the first liquid cooler, and an opposite second electrode of each semiconductor chip is in electrical contact with the second liquid cooler; and an insulating encapsulation, formed by molding the first liquid cooler, the second liquid cooler and the plurality of semiconductor chips into an insulation material, such that the first liquid cooler, the second liquid cooler and the plurality of semiconductor chips are at least partially embedded onto the insulation material.
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公开(公告)号:US10192800B2
公开(公告)日:2019-01-29
申请号:US15819579
申请日:2017-11-21
Applicant: ABB Schweiz AG
Inventor: Fabian Mohn , Paul Commin
IPC: H01L23/16 , H01L23/051 , H01L23/00
Abstract: A semiconductor device comprises two electrodes with opposite faces; a semiconductor wafer sandwiched between the two electrodes; an outer insulating ring attached to the two electrodes and surrounding the semiconductor wafer; a middle insulating ring inside the outer insulating ring and surrounding the semiconductor wafer, whereby the middle insulating ring is made of a plastics material; and an inner insulating ring inside the middle insulating ring, whereby the inner insulating ring is made of ceramics and/or glass material. Either the middle insulating ring or the inner insulating ring has a tongue and the other thereof has a groove such that the tongue fits into the groove for their rotational alignment. The middle insulating ring and the inner insulating ring have a radial opening for receiving a gate connection of the semiconductor device.
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公开(公告)号:US20200066609A1
公开(公告)日:2020-02-27
申请号:US16673201
申请日:2019-11-04
Applicant: ABB Schweiz AG , Audi AG
Inventor: Fabian Mohn
IPC: H01L23/31 , H01L23/367 , H01L21/56 , H01L21/48 , H01L23/00 , H01L25/16 , H01L23/498
Abstract: A power semiconductor module includes a substrate with a metallization layer; at least one power semiconductor chip bonded to the substrate; and a mold encapsulation partially encapsulating the semiconductor chip and the substrate; the mold encapsulation includes at least one window exposing a terminal area of the metallization layer; and a border part of the mold encapsulation between the window and a border of the substrate has a height over the substrate smaller than a maximal height of a central part of the mold encapsulation.
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公开(公告)号:US20180366400A1
公开(公告)日:2018-12-20
申请号:US16111984
申请日:2018-08-24
Applicant: ABB Schweiz AG
Inventor: Fabian Mohn , Juergen Schuderer , Felix Traub
IPC: H01L23/498 , H01L23/373 , H01L23/14 , H01L23/538 , H01L25/07 , H05K1/02 , H05K1/18 , H01L23/00
Abstract: A power module comprises at least one power semiconductor device with an electrical top contact area on a top side; and a multi-layer circuit board with multiple electrically conducting layers which are separated by multiple electrically isolating layers, the electrically isolating layers being laminated together with the electrically conducting layers; wherein the multi-layer circuit board has at least one cavity, which is opened to a top side of the multi-layer circuit board, which cavity reaches through at least two electrically conducting layers; wherein the power semiconductor device is attached with a bottom side to a bottom of the cavity; and wherein the power semiconductor device is electrically connected to a top side of the multi-layer circuit board with a conducting member bonded to the top contact area and bonded to the top side of the multi-layer circuit board.
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公开(公告)号:US20220166423A1
公开(公告)日:2022-05-26
申请号:US17101621
申请日:2020-11-23
Applicant: ABB Schweiz AG
Inventor: Giovanni Salvatore , Slavo Kicin , Fabian Mohn
Abstract: Systems, methods, techniques and apparatuses of power switches are disclosed. One exemplary embodiment is a power switch comprising an outer housing; a power electronics board disposed within the housing and including a semiconductor switch structured to selectively conduct a current between a first power terminal and a second power terminal; a first heat sink coupled to the power electronics board; a plurality of thermally conductive connectors; a second heat sink coupled to the plurality of thermally conductive connectors, a control electronics board structured to control the semiconductor switch, the control electronics board being located within an enclosure formed of the second heat sink, the plurality of thermally conductive connectors, and the power electronics board.
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公开(公告)号:US11189556B2
公开(公告)日:2021-11-30
申请号:US16419668
申请日:2019-05-22
Applicant: ABB Schweiz AG , Audi AG
Inventor: Fabian Mohn , Chunlei Liu , Jürgen Schuderer
IPC: H01L23/498 , H01L21/48 , H01L21/56 , H01L23/31 , H01L23/495
Abstract: A semi-manufactured power semiconductor module includes a substrate for bonding at least one power semiconductor chip; a first leadframe bonded to the substrate and providing power terminals; and a second leadframe bonded to the substrate and providing auxiliary terminals; wherein the first leadframe and/or the second leadframe include an interlocking element adapted for aligning the first leadframe and the second leadframe with respect to each other and/or with respect to a mold for molding an encapsulation around the substrate, the first leadframe and the second leadframe.
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