Abstract:
A power semiconductor device is provided comprising a wafer, wherein a passivation layer structure is formed at least on a portion of a surface of the wafer and the passivation layer structure comprises in an order from the surface of the wafer in a direction away from the wafer a semi-insulating layer (13), a silicon nitride layer, an undoped silicate glass layer (16) and an organic dielectric layer (17). The silicon nitride layer has a layer thickness of at least 0.5 µm. The organic dielectric layer (17) is attached to the undoped silicate glass layer (16) and the undoped silicate glass layer (16) is attached to the silicon nitride layer.