公开(公告)号：EP2234144B1

公开(公告)日：2018-08-22

申请号：EP10155457.4

申请日：2010-03-04

Applicant: ABB Schweiz AG

Inventor： Vobecky, Jan ,  Rahimo, Munaf

IPC: H01L21/266 ,  H01L21/265 ,  H01L21/22

CPC classification number: H01L21/221 ,  H01L21/26506 ,  H01L21/266

Abstract: A method for manufacturing a power semiconductor device, which comprises a first electrical contact (2) on a first main side (21) and a second electrical contact (3) on a second main side (31) opposite the first main side (21) and at least a two-layer structure with layers of different conductivity types, comprises at least the following manufacturing steps: an n doped wafer (1) is provided, a surface layer (4, 4', 4", 4'") of palladium particles is created on the first main side (21), the wafer (1) is irradiated (5) on the first main side (21) with ions, afterwards the palladium particles are diffused (41) into the wafer at a temperature of not more than 750 °C, by which diffusion a first p doped layer (7) is created, afterwards the first and second electrical contacts (2, 3) are created, characterized in that at least the step of the irradiation (5) with ions is performed through a mask (45).

公开(公告)号：EP3285290A1

公开(公告)日：2018-02-21

申请号：EP16184202.6

申请日：2016-08-15

Applicant: ABB Schweiz AG

Inventor： Papadopoulos, Charalampos ,  Rahimo, Munaf

IPC: H01L23/31 ,  H01L29/40 ,  H01L29/06 ,  H01L29/868 ,  H01L21/329

CPC classification number: H01L23/3171 ,  H01L21/02167 ,  H01L21/0217 ,  H01L23/3192 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/408 ,  H01L29/6606 ,  H01L29/739 ,  H01L29/7811 ,  H01L29/8611

Abstract: A power semiconductor device is provided comprising a wafer, wherein a passivation layer structure is formed at least on a portion of a surface of the wafer and the passivation layer structure comprises in an order from the surface of the wafer in a direction away from the wafer a semi-insulating layer (13), a silicon nitride layer, an undoped silicate glass layer (16) and an organic dielectric layer (17). The silicon nitride layer has a layer thickness of at least 0.5 µm. The organic dielectric layer (17) is attached to the undoped silicate glass layer (16) and the undoped silicate glass layer (16) is attached to the silicon nitride layer.

Abstract translation: 提供了一种包括晶片的功率半导体器件，其中至少在所述晶片的一部分表面上形成钝化层结构，并且所述钝化层结构从所述晶片的表面沿远离所述晶片的方向 半绝缘层（13），氮化硅层，未掺杂的硅酸盐玻璃层（16）和有机介电层（17）。 氮化硅层具有至少0.5μm的层厚度。 有机介电层（17）附着到未掺杂的硅酸盐玻璃层（16），未掺杂的硅酸盐玻璃层（16）附着到氮化硅层。

公开(公告)号：EP3176812A1

公开(公告)日：2017-06-07

申请号：EP15197558.8

申请日：2015-12-02

Applicant: ABB Schweiz AG

Inventor： Bartolf, Holger ,  Rahimo, Munaf ,  Knoll, Lars ,  Mihaila, Andrei ,  Minamisawa, Renato

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/739 ,  H01L29/10 ,  H01L29/16

CPC classification number: H01L29/7802 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66068 ,  H01L29/7395

Abstract: A wide bandgap semiconductor device is provided comprising an (n-) doped drift layer between a first main side (20) and a second main side (22). On the first main side (20), two n doped source regions (3, 3') which are laterally surrounded by p doped channel layers (4, 4') having a channel layer depth (40). A p+ doped well layer (5) having a well layer depth (50), which is at least as large as the channel layer depth (40) is arranged at the bottom of the source regions 3, 3'. A p++ doped plug (6) having a plug depth (60), which is as least as great as the well layer depth (50), and having a higher doping concentration than the well layer (5), is arranged between the two source regions (3, 3'). On the first side (12), a first main electrode (9) contacts as an ohmic contact at least the two source regions (3, 3') and the plug (6).

Abstract translation: 提供宽带隙半导体器件，其包括在第一主侧（20）和第二主侧（22）之间的（n-）掺杂漂移层。 在第一主侧（20）上，由p沟道层深度（40）的p掺杂沟道层（4,4'）横向围绕的两个n掺杂源极区（3,3'）。 具有至少与沟道层深度（40）一样大的阱层深度（50）的p +掺杂阱层（5）被布置在源极区域3,3'的底部。 具有至少与阱层深度（50）一样大的插塞深度（60）并且具有比阱层（5）更高的掺杂浓度的p ++掺杂插塞（6）被布置在两个源极 区域（3,3'）。 在第一侧（12）上，第一主电极（9）至少作为欧姆接触接触至少两个源区（3,3'）和插塞（6）。

公开(公告)号：EP3285290B1

公开(公告)日：2019-03-06

申请号：EP16184202.6

申请日：2016-08-15

Applicant: ABB Schweiz AG

Inventor： Papadopoulos, Charalampos ,  Rahimo, Munaf

IPC: H01L23/31 ,  H01L29/40 ,  H01L29/06 ,  H01L29/868 ,  H01L21/329

公开(公告)号：EP3240040A1

公开(公告)日：2017-11-01

申请号：EP16167002.1

申请日：2016-04-26

Applicant: ABB Schweiz AG

Inventor： Kopta, Arnost ,  Corvasce, Chiara ,  Rahimo, Munaf ,  Matthias, Sven ,  Janisch, Wolfgang

IPC: H01L29/739 ,  H01L29/66 ,  H01L29/08

CPC classification number: H01L29/7397 ,  H01L29/0834 ,  H01L29/36 ,  H01L29/66348

Abstract: An insulated gate bipolar is produced, wherein the following steps are performed:
(a) providing a lowly n doped substrate (1) having an emitter side (20) and a collector side (27),
(b) forming n and p doped layers on the emitter side (20),
(c) thinning the substrate (1) on the collector side (27),
(d) implanting an n first dopant (82) on the collector side (27) into a depth of at most 2 µm,
(e) forming a first buffer layer (8) by annealing the first dopant (82),
(f) applying a surface layer comprising an n second dopant on top of the collector side (27),
(g) forming a second buffer layer (9) by annealing the second dopant, wherein the second buffer layer (9) having a lower maximum doping concentration than the first buffer layer (8),
(h) applying a p third dopant at the collector side (27),
(i) forming a collector layer (6) by annealing the third dopant.

Abstract translation: 制造绝缘栅双极型，其中执行以下步骤：（a）提供具有发射极侧（20）和集电极侧（27）的低n型掺杂衬底（1），（b）形成n和p掺杂层 在发射极侧（20）上，（c）在集电极侧（27）上使衬底（1）变薄，（d）在集电极侧（27）注入n型第一掺杂剂（82），深度至多为2 （e）通过退火所述第一掺杂剂（82）形成第一缓冲层（8），（f）在所述集电极侧（27）的顶部上施加包含n第二掺杂剂的表面层，（g）形成第二缓冲层 其中所述第二缓冲层（9）具有比所述第一缓冲层（8）更低的最大掺杂浓度，（h）在所述集电极侧（27）施加第三掺杂剂，（ i）通过退火第三掺杂剂形成集电极层（6）。

公开(公告)号：EP3232470A1

公开(公告)日：2017-10-18

申请号：EP16165167.4

申请日：2016-04-13

Applicant: ABB Schweiz AG

Inventor： Agostini, Bruno ,  Torresin, Daniele ,  Agostini, Francesco ,  Habert, Mathieu ,  Rahimo, Munaf

IPC: H01L23/427 ,  H01L23/473 ,  F25B25/00 ,  H01L29/16 ,  H01L29/20 ,  H01L29/22

CPC classification number: H01L23/427 ,  F25B25/005 ,  H01L23/473 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/22 ,  H01L29/7393 ,  H01L29/78 ,  H05K7/20936

Abstract: A power device (10) comprises at least one power semiconductor module (12) comprising a wide bandgap semiconductor element (18); and a cooling system (16) for actively cooling the wide bandgap semiconductor element (18) with a cooling medium, wherein the cooling system (16) comprises a refrigeration device (40) for lowering a temperature of the cooling medium below an ambient temperature of the power device (10); wherein the cooling system (16) is adapted for lowering the temperature of the cooling medium in such a way that a temperature of the wide bandgap semiconductor (18) element is below 100° C.

Abstract translation: 功率器件（10）包括至少一个功率半导体模块（12），该功率半导体模块（12）包括宽带隙半导体元件（18）; 以及用冷却介质主动冷却宽带隙半导体元件（18）的冷却系统（16），其中冷却系统（16）包括用于将冷却介质的温度降低至低于环境温度的制冷设备（40） 该功率装置​​（10）; 其中所述冷却系统（16）适于以这样的方式降低所述冷却介质的温度，使得所述宽带隙半导体（18）元件的温度低于100℃

公开(公告)号：EP3232470B1

公开(公告)日：2019-01-02

申请号：EP16165167.4

申请日：2016-04-13

Applicant: ABB Schweiz AG

Inventor： Agostini, Bruno ,  Torresin, Daniele ,  Agostini, Francesco ,  Habert, Mathieu ,  Rahimo, Munaf

IPC: H01L23/427 ,  H01L23/473 ,  F25B25/00 ,  H01L29/16 ,  H01L29/20 ,  H01L29/22

公开(公告)号：EP2960941B1

公开(公告)日：2017-01-04

申请号：EP14174099.3

申请日：2014-06-26

Applicant: ABB Schweiz AG

Inventor： Rahimo, Munaf ,  Arnold, Martin ,  Vobecky, Jan ,  Vemulapati, Umamaheswara

IPC: H01L29/74 ,  H01L29/744

CPC classification number: H01L29/7416 ,  H01L27/0664 ,  H01L29/744

公开(公告)号：EP1429391A1

公开(公告)日：2004-06-16

申请号：EP02406086.5

申请日：2002-12-10

Applicant: ABB Schweiz AG

Inventor： Rahimo, Munaf ,  Von Arx, Christoph

IPC: H01L29/739 ,  H01L21/331 ,  H01L29/423 ,  H01L29/417

CPC classification number: H01L29/0696 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/423 ,  H01L29/4238 ,  H01L29/6634 ,  H01L29/7396

Abstract: An insulated gate semiconductor device comprising a semiconductor substrate (1) having a top surface and an insulated gate (21,22) formed on the top surface from a layered structure (2) that comprises at least one electrically insulating layer (22), wherein at least one strip (41,42) of the layered structure (2) is disposed on an area of the top surface between an edge of the insulated gate (21,22) and a first main contact (6).
A manufacturing method for an insulated gate semiconductor device comprising the steps of forming a cell window (3) in said layered structure (2), forming at least one process mask (51) that partially covers the cell window (3) and extends to at least partially cover said at least one strip (41,42) of the layered structure, said at least one strip (41,42) serving as an edge for the at least one process mask (51).

Abstract translation: 一种绝缘栅极半导体器件，包括具有顶表面的半导体衬底（1）和形成在包括至少一个电绝缘层（22）的层状结构（2）的顶表面上的绝缘栅极（21,22），其中 所述层状结构（2）的至少一个条带（41,42）设置在所述绝缘栅极（21,22）的边缘与第一主触头（6）之间的所述顶表面的区域上。 一种用于绝缘栅极半导体器件的制造方法，包括以下步骤：在所述层状结构（2）中形成电池窗（3），形成部分覆盖电池窗（3）的至少一个处理掩模（51） 并且延伸至至少部分地覆盖所述分层结构的所述至少一个条带（41,42），所述至少一个条带（41,42）用作所述至少一个处理掩模（51）的边缘。