公开(公告)号：EP1429391A1

公开(公告)日：2004-06-16

申请号：EP02406086.5

申请日：2002-12-10

Applicant: ABB Schweiz AG

Inventor： Rahimo, Munaf ,  Von Arx, Christoph

IPC: H01L29/739 ,  H01L21/331 ,  H01L29/423 ,  H01L29/417

CPC classification number: H01L29/0696 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/423 ,  H01L29/4238 ,  H01L29/6634 ,  H01L29/7396

Abstract: An insulated gate semiconductor device comprising a semiconductor substrate (1) having a top surface and an insulated gate (21,22) formed on the top surface from a layered structure (2) that comprises at least one electrically insulating layer (22), wherein at least one strip (41,42) of the layered structure (2) is disposed on an area of the top surface between an edge of the insulated gate (21,22) and a first main contact (6).
A manufacturing method for an insulated gate semiconductor device comprising the steps of forming a cell window (3) in said layered structure (2), forming at least one process mask (51) that partially covers the cell window (3) and extends to at least partially cover said at least one strip (41,42) of the layered structure, said at least one strip (41,42) serving as an edge for the at least one process mask (51).

Abstract translation: 一种绝缘栅极半导体器件，包括具有顶表面的半导体衬底（1）和形成在包括至少一个电绝缘层（22）的层状结构（2）的顶表面上的绝缘栅极（21,22），其中 所述层状结构（2）的至少一个条带（41,42）设置在所述绝缘栅极（21,22）的边缘与第一主触头（6）之间的所述顶表面的区域上。 一种用于绝缘栅极半导体器件的制造方法，包括以下步骤：在所述层状结构（2）中形成电池窗（3），形成部分覆盖电池窗（3）的至少一个处理掩模（51） 并且延伸至至少部分地覆盖所述分层结构的所述至少一个条带（41,42），所述至少一个条带（41,42）用作所述至少一个处理掩模（51）的边缘。