公开(公告)号：WO2004053885A1

公开(公告)日：2004-06-24

申请号：PCT/US2003/023083

申请日：2003-07-24

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： LE, Binh, Q. ,  ACHTER, Michael ,  CLEVELAND, Lee

IPC: G11C16/26

CPC classification number: G11C16/26 ,  G11C16/0491

Abstract: A memory circuit arrangement for sensing current in a target cell (305) during a read operation is disclosed. According to one exemplary embodiment, the memory circuit arrangement comprises the target cell (305) and a first neighboring cell (355) adjacent to the target cell (305). The first target cell (305) has a first bit line (316) connected to ground (365); the target cell (305) also has a second bit line (321) connected to a sensing circuit (360). The first neighboring cell (355) shares the second bit line (321) with the target cell (305); the first neighboring cell (355) also has a third bit line (341) connected to the sensing circuit (360) during the read operation. The memory circuit arrangement results in increased error margins in a fast and accurate manner during the read operation of the target cell (305).

Abstract translation: 公开了一种用于在读取操作期间感测目标单元（305）中的电流的存储器电路装置。 根据一个示例性实施例，存储器电路装置包括目标单元（305）和与目标单元（305）相邻的第一相邻单元（355）。 第一目标单元（305）具有连接到地（365）的第一位线（316）。 目标单元（305）还具有连接到感测电路（360）的第二位线（321）。 第一相邻小区（355）与目标小区（305）共享第二位线（321）; 在读取操作期间，第一相邻单元（355）还具有连接到感测电路（360）的第三位线（341）。 存储器电路装置在目标单元（305）的读取操作期间以快速和准确的方式导致增加的误差容限。

公开(公告)号：WO2004072982A1

公开(公告)日：2004-08-26

申请号：PCT/US2004/000498

申请日：2004-01-08

Applicant: ADVANCED MICRO DEVICES, INC. ,  LE, Binh, Quang ,  ACHTER, Michael ,  CLEVELAND, Lee ,  CHEN, Pau-Ling

Inventor： LE, Binh, Quang ,  ACHTER, Michael ,  CLEVELAND, Lee ,  CHEN, Pau-Ling

IPC: G11C17/12

CPC classification number: G11C16/0491 ,  G11C16/24 ,  G11C16/26

Abstract: A selection circuit for sensing current in a target cell (305) during a memory read operation is disclosed. According to one embodiment, the selection circuit comprises a sensing circuit selector (364) connected to a sensing circuit (360) and a ground selector (362) connected to ground (365). The ground selector (362) connects a first bit line (316) of the target cell to ground, and the sensing circuit selector (364) connects a second bit line (321) of the target cell (305) to the sensing circuit (360). The sensing circuit selector (364) also connects a third bit line (341) of a first neighboring cell (355) to the sensing circuit (360). The first neighboring cell (355) shares the second bit line (321) with the target cell (305).

Abstract translation: 公开了一种用于在存储器读取操作期间感测目标单元（305）中的电流的选择电路。 根据一个实施例，选择电路包括连接到感测电路（360）的感测电路选择器（364）和连接到地线（365）的接地选择器（362）。 接地选择器（362）将目标单元的第一位线（316）连接到地，并且感测电路选择器（364）将目标单元（305）的第二位线（321）连接到感测电路（360） ）。 感测电路选择器（364）还将第一相邻单元（355）的第三位线（341）连接到感测电路（360）。 第一相邻小区（355）与目标小区（305）共享第二位线（321）。

公开(公告)号：EP1573746A1

公开(公告)日：2005-09-14

申请号：EP03812759.3

申请日：2003-07-24

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： LE, Binh, Q. ,  ACHTER, Michael ,  CLEVELAND, Lee

IPC: G11C16/26 ,  G11C16/04

CPC classification number: G11C16/26 ,  G11C16/0491

Abstract: A memory circuit arrangement for sensing current in a target cell (305) during a read operation is disclosed. According to one exemplary embodiment, the memory circuit arrangement comprises the target cell (305) and a first neighboring cell (355) adjacent to the target cell (305). The first target cell (305) has a first bit line (316) connected to ground (365); the target cell (305) also has a second bit line (321) connected to a sensing circuit (360). The first neighboring cell (355) shares the second bit line (321) with the target cell (305); the first neighboring cell (355) also has a third bit line (341) connected to the sensing circuit (360) during the read operation. The memory circuit arrangement results in increased error margins in a fast and accurate manner during the read operation of the target cell (305).