公开(公告)号：WO1997015928A1

公开(公告)日：1997-05-01

申请号：PCT/US1996010720

申请日：1996-06-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  CLEVELAND, Lee ,  CHANG, Chung, K. ,  TANG, Yuan ,  LEONG, Nancy ,  FLIESLER, Michael ,  KUO, Tiao-Hua

IPC: G11C16/06

CPC classification number: G11C16/3409 ,  G11C16/3404 ,  G11C16/3445

Abstract: An integrated circuit including an array of flash EEPROM memory cells wherein overerase correction is provided after application of each erase pulse.

Abstract translation: 一种包括闪存EEPROM存储单元阵列的集成电路，其中在施加每个擦除脉冲之后提供过电压校正。

公开(公告)号：WO2004095462A1

公开(公告)日：2004-11-04

申请号：PCT/US2004/007188

申请日：2004-03-08

Applicant: ADVANCED MICRO DEVICES, INC. ,  LE, Binh Quang ,  LY, Cathy, Thuvan ,  CLEVELAND, Lee ,  CHEN, Pau-ling

Inventor： LE, Binh Quang ,  LY, Cathy, Thuvan ,  CLEVELAND, Lee ,  CHEN, Pau-ling

IPC: G11C5/14

CPC classification number: G11C5/145 ,  G11C8/08

Abstract: Flash memory array systems (340, 450, 500, 1200) and methods (1300) are disclosed for producing a regulated boosted word line voltage (348, 452, 532, 1235) for read operations. The system comprises a multi-stage voltage boost circuit (347, 500) operable to receive a supply voltage (343) and one or more output signals (345, 346, 525, 526) from a supply voltage detection circuit (342) to generate the boosted word line voltage (348, 532) having a value greater than the supply voltage (540). The voltage boost circuit comprises a precharge circuit (522) and a plurality of boost cells (540) connected to a common node (532) of the boosted word line, and a timing control circuit (510). The stages (1210, 1220, 1230) of the plurality of boost cells are coupled in series for charge sharing between the stages, and couple a predetermined number of boost cells to the boosted word line common node (532) to provide an intermediate voltage to the boosted word line during the pre-boost timing (747), thereby anticipating a final boosted word line voltage (770, 770a, 770b) provided during the boost timing (745). The voltage boost circuit is operable to receive the one or more output signals from the supply voltage detection circuit and alter a boost gain of the multi-stage voltage boost circuit based on the one or more output signals, thereby causing the boosted word line voltage to be substantially independent of the supply voltage value.

Abstract translation: 公开了用于产生用于读取操作的调节升压的字线电压（348,452,532,1235）的闪存阵列系统（340,450,500,1200）和方法（1300）。 该系统包括可操作以从电源电压检测电路（342）接收电源电压（343）和一个或多个输出信号（345,346,525,526）的多级升压电路（347,500），以产生 所述升压的字线电压（348,532）具有大于所述电源电压（540）的值。 升压电路包括预充电电路（522）和连接到升压字线的公共节点（532）的多个升压单元（540）和定时控制电路（510）。 多个升压单元的级（1210,1220,1230）被串联耦合以用于级之间的电荷共享，并且将预定数量的升压单元耦合到升压的字线公共节点（532）以提供中间电压 在预升压时序（747）期间的升压字线，从而预期在升压定时（745）期间提供的最后升高的字线电压（770,770a，770b）。 电压升压电路可操作以从电源电压检测电路接收一个或多个输出信号，并且基于一个或多个输出信号改变多级升压电路的升压增益，由此使升压的字线电压 基本上不依赖于电源电压值。

公开(公告)号：WO2004072982A1

公开(公告)日：2004-08-26

申请号：PCT/US2004/000498

申请日：2004-01-08

Applicant: ADVANCED MICRO DEVICES, INC. ,  LE, Binh, Quang ,  ACHTER, Michael ,  CLEVELAND, Lee ,  CHEN, Pau-Ling

Inventor： LE, Binh, Quang ,  ACHTER, Michael ,  CLEVELAND, Lee ,  CHEN, Pau-Ling

IPC: G11C17/12

CPC classification number: G11C16/0491 ,  G11C16/24 ,  G11C16/26

Abstract: A selection circuit for sensing current in a target cell (305) during a memory read operation is disclosed. According to one embodiment, the selection circuit comprises a sensing circuit selector (364) connected to a sensing circuit (360) and a ground selector (362) connected to ground (365). The ground selector (362) connects a first bit line (316) of the target cell to ground, and the sensing circuit selector (364) connects a second bit line (321) of the target cell (305) to the sensing circuit (360). The sensing circuit selector (364) also connects a third bit line (341) of a first neighboring cell (355) to the sensing circuit (360). The first neighboring cell (355) shares the second bit line (321) with the target cell (305).

Abstract translation: 公开了一种用于在存储器读取操作期间感测目标单元（305）中的电流的选择电路。 根据一个实施例，选择电路包括连接到感测电路（360）的感测电路选择器（364）和连接到地线（365）的接地选择器（362）。 接地选择器（362）将目标单元的第一位线（316）连接到地，并且感测电路选择器（364）将目标单元（305）的第二位线（321）连接到感测电路（360） ）。 感测电路选择器（364）还将第一相邻单元（355）的第三位线（341）连接到感测电路（360）。 第一相邻小区（355）与目标小区（305）共享第二位线（321）。

公开(公告)号：WO2002015193A3

公开(公告)日：2002-02-21

申请号：PCT/US2001/024024

申请日：2001-07-30

Applicant: ADVANCED MICRO DEVICES, INC. ,  FUJITSU LIMITED

Inventor： AKAOGI, Takao ,  NGUYEN, Kendra ,  KIM, Yong ,  CLEVELAND, Lee

IPC: G11C8/08

Abstract: A burst read mode operation is provided that boosts the voltage of a word line (12) while the bit lines of the row are selected for reading. When the column group address bits (35) read the last column group of cells in the row, a pulse signal (96) is generated which temporarily reduces the boosted voltage to allow the X-decoder (14) to select the next work line. An alternative delay element (100) is also provided which generates an ATD pulse (64) with a longer duration when the column group address bits (35) are at the end of a row and a shorter duration pulse at other times.

公开(公告)号：WO2004053885A1

公开(公告)日：2004-06-24

申请号：PCT/US2003/023083

申请日：2003-07-24

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： LE, Binh, Q. ,  ACHTER, Michael ,  CLEVELAND, Lee

IPC: G11C16/26

CPC classification number: G11C16/26 ,  G11C16/0491

Abstract: A memory circuit arrangement for sensing current in a target cell (305) during a read operation is disclosed. According to one exemplary embodiment, the memory circuit arrangement comprises the target cell (305) and a first neighboring cell (355) adjacent to the target cell (305). The first target cell (305) has a first bit line (316) connected to ground (365); the target cell (305) also has a second bit line (321) connected to a sensing circuit (360). The first neighboring cell (355) shares the second bit line (321) with the target cell (305); the first neighboring cell (355) also has a third bit line (341) connected to the sensing circuit (360) during the read operation. The memory circuit arrangement results in increased error margins in a fast and accurate manner during the read operation of the target cell (305).

Abstract translation: 公开了一种用于在读取操作期间感测目标单元（305）中的电流的存储器电路装置。 根据一个示例性实施例，存储器电路装置包括目标单元（305）和与目标单元（305）相邻的第一相邻单元（355）。 第一目标单元（305）具有连接到地（365）的第一位线（316）。 目标单元（305）还具有连接到感测电路（360）的第二位线（321）。 第一相邻小区（355）与目标小区（305）共享第二位线（321）; 在读取操作期间，第一相邻单元（355）还具有连接到感测电路（360）的第三位线（341）。 存储器电路装置在目标单元（305）的读取操作期间以快速和准确的方式导致增加的误差容限。

公开(公告)号：WO2004049340A1

公开(公告)日：2004-06-10

申请号：PCT/US2003/021634

申请日：2003-07-10

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： LE, Binh, Quang ,  CLEVELAND, Lee ,  CHEN, Pau-Ling

IPC: G11C7/12

CPC classification number: G11C16/24 ,  G11C7/067

Abstract: A cascode amplifier circuit (205), which generates a fast, stable and accurate bit line voltage (230), is disclosed. According to one exemplary embodiment, the cascode amplifier circuit (205) comprises a transistor (210) having a source connected to a bit line voltage (230) and a drain connected to an output voltage (225). The cascode amplifier circuit (205) also comprises a differential circuit (212) having an inverting input (215) connected to the bit line voltage (230), a non-inverting input connected to a reference voltage (202), and an output (280) connected to a gate of the first transistor (210). The operation of the transistor (210) and the differential circuit (212) generate a fast, stable the accurate bit line voltage (230).

Abstract translation: 公开了一种产生快速，稳定和精确的位线电压（230）的共源共栅放大器电路（205）。 根据一个示例性实施例，共射共基放大器电路（205）包括具有连接到位线电压（230）的源极和连接到输出电压（225）的漏极的晶体管（210）。 共源共栅放大器电路（205）还包括差分电路（212），其具有连接到位线电压（230）的反相输入（215），连接到参考电压（202）的非反相输入和输出（ 280）连接到第一晶体管（210）的栅极。 晶体管（210）和差分电路（212）的操作产生快速，稳定的精确位线电压（230）。

公开(公告)号：WO2002089144A1

公开(公告)日：2002-11-07

申请号：PCT/US2001/043730

申请日：2001-11-14

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： FASTOW, Richard, M. ,  HADDAD, Sameer ,  CLEVELAND, Lee

IPC: G11C16/34

CPC classification number: G11C16/3422 ,  G11C16/344 ,  G11C16/3445

Abstract: A technique is provided for reducing column leakage in a flash EEPROM device (10) during an erase verification process, thereby preventing false verifies. The technique has application in NOR arrays or other types of arrays in which a number of cells (100) are connected in parallel. The technique operates by reducing the leakage of the unselected cells in parallel to the selected cell being verified, thereby preventing false verifies. The technique can also be used in conjunction with other techniques for reducing column leakage, such as soft programming, automatic programming disturb erase (APDE), or various other V th compacting schemes.

Abstract translation: 提供了一种用于在擦除验证过程期间减少快闪EEPROM装置（10）中的列泄漏的技术，从而防止虚假验证。 该技术在NOR阵列或其他类型的阵列中的应用，其中多个单元（100）并联连接。 该技术通过减少未被选择的小区的泄漏与所验证的所选择的小区并行地进行操作，从而防止虚假验证。 该技术还可以与减少列泄漏的其他技术结合使用，例如软编程，自动编程干扰擦除（APDE）或各种其他Vth压缩方案。

公开(公告)号：EP0857346B1

公开(公告)日：1999-08-11

申请号：EP96921742.1

申请日：1996-06-21

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： CLEVELAND, Lee ,  CHANG, Chung, K. ,  TANG, Yuan ,  LEONG, Nancy ,  FLIESLER, Michael ,  KUO, Tiao-Hua

IPC: G11C16/06

CPC classification number: G11C16/3409 ,  G11C16/3404 ,  G11C16/3445

Abstract: An integrated circuit including an array of flash EEPROM memory cells wherein overerase correction is provided after application of each erase pulse.

公开(公告)号：EP1290559B1

公开(公告)日：2004-03-24

申请号：EP01939217.4

申请日：2001-05-21

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： AL-SHAMMA, Ali ,  CLEVELAND, Lee

IPC: G06F11/20 ,  G11C8/16 ,  G11C15/04

CPC classification number: G11C29/789 ,  G11C8/16 ,  G11C15/046

Abstract: A flash memory having redundancy content addressable memory (CAM) circuitry (106) is described. The flash memory is capable of substituting a second memory cell for an inoperative memory cell. The flash memory includes a primary array (118, 120, 122, 124, 134, 136, 138, 140) of memory cells, a redundant array (126, 128, 130, 132, 142, 144, 146, 148) of memory cells, and the redundancy CAM circuitry (106). The redundancy CAM circuitry (106) includes a plurality of dual-ported CAM stages (200). Each CAM stage (200) includes a CAM cell (202), a write data bus (204) coupled to the CAM cell (202), and a read data bus (206) coupled to the CAM cell (202). The CAM cell (202) stores information regarding a location of an inoperative memory cell in the primary array (118, 120, 122, 124, 134, 138, 140). The inoperative memory cell requires a substitution with a second memory cell in the redundant array (126, 128, 130, 132, 142, 144, 146, 148). The write data bus (204) produces the information from the CAM cell (202) responsively to a write select signal (WSELm). The write select signal (WSELm) is indicative of a write operation to be performed at memory cell locations in the primary array (18, 120, 122, 124, 134, 136, 138, 140). The read data bus (206) produces the information from the CAM cell (202) responsively to a read select signal (RSELm). The read select signal (RSELm) is indicative of a read operation to be performed at memory cell locations in the primary array (118, 120, 122, 124, 134, 136, 138, 140).

公开(公告)号：EP1295294A2

公开(公告)日：2003-03-26

申请号：EP01937634.2

申请日：2001-05-21

Applicant: ADVANCED MICRO DEVICES INC. ,  FUJITSU LIMITED

Inventor： AKAOGI, Takao ,  CLEVELAND, Lee ,  NGUYEN, Kendra

IPC: G11C7/10

CPC classification number: G11C7/1018 ,  G11C7/1072

Abstract: A burst mode architecture to provide burst mode access to a plurality of data words in a flash memory is described. The burst mode architecture includes a first circuit (216, 220), a control circuit (210) coupled to the first circuit (216, 220), and a data buffer (236, 238) selectively coupled to the first circuit (216, 220) by the control circuit (210). The first circuit (216, 220) accesses a plurality of data words, beginning with an initial access of a first data word and a second data word. The control circuit (210) generates a timing signal having pulses and a second signal. The second signal is generated upon completion of the initial access of the first data word and the second data word. The first circuit (216, 220) follows the initial access with subsequent accesses of the plurality of data words responsively to the second signal and the timing signal. The data buffer has an output and procedures the first data word at the output and successively produces, with each successive pulse of the timing signal following an initial period of time, the second data word, and subsequent data words at the output. The subsequent data words correspond to the subsequent accesses of the plurality of data words.