公开(公告)号：WO1998014023A1

公开(公告)日：1998-04-02

申请号：PCT/US1997017150

申请日：1997-09-24

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  ASGHAR, Saf, M. ,  SPAK, Michael, E.

IPC: H04Q07/32

CPC classification number: H04W88/02 ,  H04B1/0003 ,  H04B1/16 ,  H04B1/30 ,  H04B1/406 ,  Y02D70/00 ,  Y02D70/1222 ,  Y02D70/142 ,  Y02D70/40

Abstract: A configurable multiprocessor communications architecture which performs digital communications functions and which is configurable for different digital communications standards, such as various digital cellular standards. In the preferred embodiment, the multiprocessor architecture includes two or more digital signal processing cores (212), a microcontroller or microscheduler (222), a voice coder/decoder (codec), and a relatively low performance central processing unit (CPU) (250). Each of the above devices are coupled to a system memory (202). The general purpose CPU preferably performs user interface functions and overall communications management functions. A CPU local memory (262) and various peripheral devices (264) are coupled through a CPU local bus (260) to the CPU, and these devices are accessible to the CPU without the CPU having to access the main system bus. A dual port bus arbiter (252) is preferably coupled between the CPU and the system bus (214) and controls access to the system bus and the CPU local bus. The microscheduler operates to schedule operations and/or functions, as well as dynamically control the clock rates, of each of the DSPs and the hardware acceleration logic (240) to achieve the desired throughput while minimizing power consumption. The present invention thus provides a single architecture which has simplified configurability for different digital standards. The configurable digital communications architecture simplifies design and manufacturing costs and provides improved performance over prior designs.

Abstract translation: 一种可配置的多处理器通信架构，其执行数字通信功能并且可配置用于不同数字通信标准，例如各种数字蜂窝标准。 在优选实施例中，多处理器架构包括两个或多个数字信号处理核心（212），微控制器或微处理器（222），语音编码器/解码器（编解码器）和相对低性能的中央处理器（CPU）（250） ）。 上述每个设备耦合到系统存储器（202）。 通用CPU优选地执行用户界面功能和整体通信管理功能。 CPU本地存储器（262）和各种外围设备（264）通过CPU本地总线（260）耦合到CPU，并且CPU可访问这些设备，而CPU不必访问主系统总线。 双端口总线仲裁器（252）优选地耦合在CPU和系统总线（214）之间，并控制对系统总线和CPU本地总线的访问。 微调计器操作以调度操作和/或功能，以及动态地控制每个DSP和硬件加速逻辑（240）的时钟速率，以实现期望的吞吐量同时最小化功耗。 因此，本发明提供了一种具有简化的用于不同数字标准的可配置性的单一架构。 可配置的数字通信架构简化了设计和制造成本，并提供了比以前的设计更好的性能。

公开(公告)号：EP0928550A1

公开(公告)日：1999-07-14

申请号：EP97945275.0

申请日：1997-09-24

Applicant: Advanced Micro Devices, Inc.

Inventor： ASGHAR, Saf, M. ,  SPAK, Michael E.

IPC: H04B1 ,  H04W88

CPC classification number: H04W88/02 ,  H04B1/0003 ,  H04B1/16 ,  H04B1/30 ,  H04B1/406 ,  Y02D70/00 ,  Y02D70/1222 ,  Y02D70/142 ,  Y02D70/40

Abstract: A configurable multiprocessor communications architecture which performs digital communications functions and which is configurable for different digital communications standards, such as various digital cellular standards. In the preferred embodiment, the multiprocessor architecture includes two or more digital signal processing cores, a microcontroller or micro-scheduler, a voice coder/decoder (codec), and a relatively low performance central processing unit (CPU). Each of the above devices are coupled to a system memory. The general purpose CPU preferably performs user interface functions and overall communications management functions. A CPU local memory and various peripheral devices are coupled through a CPU local bus to the CPU, and these devices are accessible to the CPU without the CPU having to access the main system bus. A dual port bus arbiter is preferably coupled between the CPU and the system bus and controls access to the system bus and the CPU local bus. The micro-scheduler operates to schedule operations and/or functions, as well as dynamically control the clock rates, of each of the DSPs and the hardware acceleration logic to achieve the desired throughput while minimizing power consumption. The present invention thus provides a single architecture which has simplified configurability for different digital standards. The configurable digital communications architecture simplifies design and manufacturing costs and provides improved performance over prior designs.