公开(公告)号：WO2003034240A1

公开(公告)日：2003-04-24

申请号：PCT/US2002/026884

申请日：2002-08-22

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ASKAR, Tahsin ,  HEWITT, Larry, D. ,  CHAMBERS, Eric, G.

IPC: G06F13/12

CPC classification number: G06F13/128

Abstract: A peripheral interface circuit (350) for an I/O node of a computer system. A peripheral interface circuit for an input/output node of a computer system includes a first buffer circuit (390), a second buffer circuit (5300) and a bus interface circuit (490). The first buffer circuit receives packet commands and may include a first plurality of buffers each corresponding to a respective virtual channel of a plurality of virtual channels. The second buffer circuit is coupled to receive packet commands from the bus interface circuit and may include a second plurality of buffers each corresponding to a respective virtual channel of the plurality of virtual channels. The bus interface circuit may be configured to translate selected packet commands stored in the first buffer circuit into commands suitable for transmission on a peripheral bus (560).

Abstract translation: 一种用于计算机系统的I / O节点的外围接口电路（350）。 用于计算机系统的输入/输出节点的外围接口电路包括第一缓冲电路（390），第二缓冲电路（5300）和总线接口电路（490）。 第一缓冲电路接收分组命令，并且可以包括每个对应于多个虚拟通道的相应虚拟通道的第一多个缓冲器。 第二缓冲电路被耦合以从总线接口电路接收分组命令，并且可以包括每个对应于多个虚拟通道中的相应虚拟通道的第二多个缓冲器。 总线接口电路可以被配置为将存储在第一缓冲器电路中的选择的分组命令转换成适合于在外围总线（560）上传输的命令。

公开(公告)号：WO2009025712A1

公开(公告)日：2009-02-26

申请号：PCT/US2008/009098

申请日：2008-07-28

Applicant: ADVANCED MICRO DEVICES, INC. ,  MADRID, Philip, E. ,  ASKAR, Tahsin

Inventor： MADRID, Philip, E. ,  ASKAR, Tahsin

IPC: G06F12/02 ,  G06F13/16

CPC classification number: G06F12/0215 ,  G06F13/161

Abstract: A DRAM controller (103) may be configured to re-order read/write requests to maximize the number of page hits and minimize the number of page conflicts and page misses. A three-level prediction algorithm may be performed to obtain auto-precharge prediction for each read/write request, without having to track every individual page. Instead, the DRAM controller may track the history of page activity for each bank of DRAM (105), and make a prediction to first order based history that is not bank based. The memory requests may be stored in a queue, a specified number at a time, and used to determine whether a page should be closed or left open following access to that page. If no future requests in the queue are to the given bank containing the page, recent bank history for that bank may be used to obtain a prediction whether the page should be closed or left open. If the page is not closed as a result of the determination and/or prediction, it may be left open and closed after it has remained idle a specified length of time following the last access to the page.

Abstract translation: DRAM控制器（103）可以被配置为重新排序读/写请求，以最大化页面命中的数量并且最小化页面冲突和页面错失的次数。 可以执行三电平预测算法以获得每个读/写请求的自动预充电预测，而不必跟踪每个单独的页面。 相反，DRAM控制器可以跟踪DRAM（105）的每一组的页面活动的历史，并对不是基于银行的基于第一阶的历史进行预测。 存储器请求可以一次存储在一个队列中，一个指定的数字，并且用于确定在访问该页面之后页面是应该被关闭还是保持打开。 如果队列中未来的请求不包含该页面的给定银行，则可能会使用该银行的最近银行历史记录来获取该页面是关闭还是打开的预测。 如果作为确定和/或预测的结果没有关闭页面，则可以在最后访问页面之后指定的时间长度保持空闲之后将其打开并关闭。

公开(公告)号：WO2009025714A1

公开(公告)日：2009-02-26

申请号：PCT/US2008/009102

申请日：2008-07-28

Applicant: ADVANCED MICRO DEVICES, INC. ,  ASKAR, Tahsin ,  MADRID, Philip, E.

Inventor： ASKAR, Tahsin ,  MADRID, Philip, E.

IPC: G06F13/16

CPC classification number: G06F13/161

Abstract: A method for throttling a bus, e.g. a memory bus (111), may be used to compensate for potential inaccuracy of feedback information received for monitored characteristics, e.g. temperature, reported by sensors configured in monitored devices, e.g. memory devices (105), accessed through the bus. For example, in case of a memory bus, a memory controller (103) may be configured to throttle the memory bus in a way that maximizes system performance while ensuring that the memory devices keep operating within their thermal limits. Readings obtained from the memory, or from close proximity to the memory, may indicate whether the temperature of the memory has crossed over one or more designated trip points, and one or more algorithms may be executed to perform throttling according to the readings and based on fixed and dynamic throttling modes. The memory controller may infer temperature changes taking place in the memory devices when successive readings are indicating that the temperature of the memory device has remained over a given trip point. Based on these inferences, the memory controller may then change the manner in which the bus is throttled.

Abstract translation: 一种用于扼流总线的方法，例如 存储器总线（111）可以用于补偿为监视的特性而接收的反馈信息的潜在不准确性，例如， 温度由在被监控设备中配置的传感器报告。 存储器件（105），通过总线访问。 例如，在存储器总线的情况下，存储器控制器（103）可以被配置为以使得系统性能最大化的方式来节制存储器总线，同时确保存储器件在其热限制内保持工作。 从存储器或从靠近存储器获得的读取可以指示存储器的温度是否超过一个或多个指定的跳变点，并且可以执行一个或多个算法以根据读数执行调节，并且基于 固定和动态节流模式。 当连续读数指示存储器件的温度保持在给定跳变点以上时，存储器控制器可以推断在存储器件中发生的温度变化。 基于这些推论，存储器控制器然后可以改变总线被节流的方式。

公开(公告)号：WO2022046689A1

公开(公告)日：2022-03-03

申请号：PCT/US2021/047236

申请日：2021-08-24

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ASKAR, Tahsin

IPC: G06F13/16

Abstract: A shared data transfer clock is used among double data rate memory ranks. A memory controller processes incoming memory access commands destined for at least one of a plurality of double data rate memory ranks and determines when a target DDR memory rank is out of synchronization with respect to the shared data transfer clock and a memory clock. In response to determining that the target DDR memory rank is out of synchronization, the memory controller determines whether the non-target DDR memory rank is out-of-synchronization with respect to the shared data transfer clock and the memory clock, and issues a data transfer clock synchronization command to the target DDR memory rank in response to determining that the non-target DDR memory rank is out-of-synchronization with respect to the shared data transfer clock and the memory clock.

公开(公告)号：WO2009025713A1

公开(公告)日：2009-02-26

申请号：PCT/US2008/009101

申请日：2008-07-28

Applicant: ADVANCED MICRO DEVICES, INC. ,  ASKAR, Tahsin ,  MADRID, Phillip, E.

Inventor： ASKAR, Tahsin ,  MADRID, Phillip, E.

IPC: G06F13/16

CPC classification number: G06F13/1684

Abstract: A DRAM controller (103) may comprise two sub-controllers (406, 404), each capable of handling a respective N-bit interface (e.g. 64-bit interface). Each sub-controller may also be configurable to be (2*N)-bit (e.g. 128-bit) capable with respect to control logic, for controlling a logical 128-bit data path. In ganged mode, each sub-controller may logically operate as if it were handling data in 128-bit chunks, (i.e. handling the entire 128- bit data path), while actual full bandwidth may be achieved by having one of the sub-controllers operate on commands and a first N-bit portion of each (2*N)-bit chunk of data, and having the other sub-controller operate on a "copy" of the commands with a corresponding remaining N-bit portion of each (2*N)-bit chunk of data. Once the BIOS has configured and initialized the two DRAM controllers to operate in ganged mode, the BIOS and all software may no longer need to be aware that two memory controllers are used to access a single (2*N)-bit wide channel.

Abstract translation: DRAM控制器（103）可以包括两个子控制器（406,404），每个子控制器能够处理相应的N位接口（例如，64位接口）。 每个子控制器还可以被配置为相对于控制逻辑能够（2 * N）位（例如128位），用于控制逻辑128位数据路径。 在组合模式下，每个子控制器可以在逻辑上操作，就像处理128位块中的数据一样（即处理整个128位数据路径），而实际的全带宽可以通过使其中一个子控制器 对每个（2 * N）位数据块的命令和第一N位部分进行操作，并且使另一个子控制器对命令的“复制”与每个（2×N）位数据的相应的剩余N位部分进行操作 2 * N）位数据块。 一旦BIOS配置并初始化了两个DRAM控制器以联合模式运行，则BIOS和所有软件可能不再需要注意两个存储器控制器用于访问单个（2 * N）位宽通道。

公开(公告)号：EP1436709B1

公开(公告)日：2006-04-26

申请号：EP02801621.0

申请日：2002-08-22

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ASKAR, Tahsin ,  HEWITT, Larry, D. ,  CHAMBERS, Eric, G.

IPC: G06F13/12

CPC classification number: G06F13/128

Abstract: A peripheral interface circuit (350) for an I/O node of a computer system. A peripheral interface circuit for an input/output node of a computer system includes a first buffer circuit (390), a second buffer circuit (5300) and a bus interface circuit (490). The first buffer circuit receives packet commands and may include a first plurality of buffers each corresponding to a respective virtual channel of a plurality of virtual channels. The second buffer circuit is coupled to receive packet commands from the bus interface circuit and may include a second plurality of buffers each corresponding to a respective virtual channel of the plurality of virtual channels. The bus interface circuit may be configured to translate selected packet commands stored in the first buffer circuit into commands suitable for transmission on a peripheral bus (560).

公开(公告)号：EP2191376A1

公开(公告)日：2010-06-02

申请号：EP08794791.7

申请日：2008-07-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： MADRID, Philip, E. ,  ASKAR, Tahsin

IPC: G06F12/02 ,  G06F13/16

CPC classification number: G06F12/0215 ,  G06F13/161

Abstract: A DRAM controller (103) may be configured to re-order read/write requests to maximize the number of page hits and minimize the number of page conflicts and page misses. A three-level prediction algorithm may be performed to obtain auto-precharge prediction for each read/write request, without having to track every individual page. Instead, the DRAM controller may track the history of page activity for each bank of DRAM (105), and make a prediction to first order based history that is not bank based. The memory requests may be stored in a queue, a specified number at a time, and used to determine whether a page should be closed or left open following access to that page. If no future requests in the queue are to the given bank containing the page, recent bank history for that bank may be used to obtain a prediction whether the page should be closed or left open. If the page is not closed as a result of the determination and/or prediction, it may be left open and closed after it has remained idle a specified length of time following the last access to the page.

公开(公告)号：EP1436709A1

公开(公告)日：2004-07-14

申请号：EP02801621.0

申请日：2002-08-22

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： ASKAR, Tahsin ,  HEWITT, Larry, D. ,  CHAMBERS, Eric, G.

IPC: G06F13/12

CPC classification number: G06F13/128

Abstract: A peripheral interface circuit (350) for an I/O node of a computer system. A peripheral interface circuit for an input/output node of a computer system includes a first buffer circuit (390), a second buffer circuit (5300) and a bus interface circuit (490). The first buffer circuit receives packet commands and may include a first plurality of buffers each corresponding to a respective virtual channel of a plurality of virtual channels. The second buffer circuit is coupled to receive packet commands from the bus interface circuit and may include a second plurality of buffers each corresponding to a respective virtual channel of the plurality of virtual channels. The bus interface circuit may be configured to translate selected packet commands stored in the first buffer circuit into commands suitable for transmission on a peripheral bus (560).

公开(公告)号：EP4200712A1

公开(公告)日：2023-06-28

申请号：EP21772899.7

申请日：2021-08-24

Applicant: Advanced Micro Devices, Inc.

Inventor： ASKAR, Tahsin

IPC: G06F13/16

公开(公告)号：EP2191376B1

公开(公告)日：2016-09-28

申请号：EP08794791.7

申请日：2008-07-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： MADRID, Philip, E. ,  ASKAR, Tahsin

IPC: G06F12/02 ,  G06F13/16

CPC classification number: G06F12/0215 ,  G06F13/161