公开(公告)号：WO2004099954A1

公开(公告)日：2004-11-18

申请号：PCT/US2004/000484

申请日：2004-01-09

Applicant: ADVANCED MICRO DEVICES, INC. ,  GULICK, Dale, E. ,  STRONGIN, Geoffrey, S. ,  HEWITT, Larry, D.

Inventor： GULICK, Dale, E. ,  STRONGIN, Geoffrey, S. ,  HEWITT, Larry, D.

IPC: G06F1/00

CPC classification number: G06F21/74 ,  G06F21/85 ,  G06F2221/2105

Abstract: A computer system (10, 20) including a bus bridge (121, 221, 321) for bridging transactions between a secure execution mode-capable processor (100A-B) and a security services processor (130). The bus bridge may include a transaction source detector (450), a configuration header (415) and control logic (416). The transaction source detector may receive a security initialization transaction performed as a result of execution of a security initialization instruction. Further, the transaction source detector may determine whether the secure execution mode-capable processor is a source of the security initialization transaction. The configuration header may provide storage of information associated with the security services processor. The control logic may determine whether the security services processor is coupled to the bus bridge via a non-enumerable, peripheral bus (135, 335). The control logic may also cause the configuration header to be accessible during a boot-up sequence in response to determining that the security services processor is coupled to the non-enumerable, peripheral bus.

Abstract translation: 一种计算机系统（10,20），包括用于桥接安全执行模式处理器（100A-B）和安全服务处理器（130）之间的事务的总线桥（121,221,321）。 总线桥可以包括事务源检测器（450），配置头（415）和控制逻辑（416）。 事务源检测器可以接收由于执行安全初始化指令而执行的安全初始化事务。 此外，事务源检测器可以确定具有安全执行模式的处理器是否是安全初始化事务的源。 配置头可以提供与安全服务处理器相关联的信息的存储。 控制逻辑可以确定安全服务处理器是否经由不可枚举的外围总线（135,335）耦合到总线桥。 响应于确定安全服务处理器耦合到不可枚举的外围总线，控制逻辑还可以使配置头在启动序列期间可访问。

公开(公告)号：WO1998022877A1

公开(公告)日：1998-05-28

申请号：PCT/US1997021506

申请日：1997-11-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  HEWITT, Larry, D.

IPC: G06F11/30

CPC classification number: G06F11/3027 ,  G06F11/3079 ,  G06F13/423 ,  G06F2201/81 ,  G06F2201/88

Abstract: An arrangement for monitoring clock frequency variations on a peripheral bus (211) is provided to improve operations of the peripheral device (118, 119) despite changes in the clock frequency. In one aspect of the arrangement, a processing unit (101) is coupled to a host bus (103) which in turn is coupled to a peripheral bus which is coupled to a peripheral device. A monitoring arrangement (121) is provided which detects a change in the clock frequency of the peripheral bus and determines if the frequency change exceeds a threshold associated with the peripheral device. If the threshold is exceeded, the peripheral device is informed that the clock frequency of the peripheral bus has changed. A peripheral device operating at different operating levels may use the information from the monitoring arrangement to alter the operating level of the peripheral device to conform to the new bus clock frequency.

Abstract translation: 提供了用于监视外围总线（211）上的时钟频率变化的装置，以便尽管时钟频率的改变来改善外围设备（118,119）的操作。 在该装置的一个方面，处理单元（101）耦合到主机总线（103），主机总线（103）又耦合到耦合到外围设备的外围总线。 提供了一种监视装置（121），其检测外围总线的时钟频率的变化，并确定频率变化是否超过与外围设备相关联的阈值。 如果超过阈值，则通知外围设备外围总线的时钟频率已经改变。 在不同操作级别操作的外围设备可以使用来自监视装置的信息来改变外围设备的操作级别以符合新的总线时钟频率。

公开(公告)号：WO1996015484A2

公开(公告)日：1996-05-23

申请号：PCT/US1995014254

申请日：1995-11-02

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  HEWITT, Larry, D. ,  BLUMENTHAL, Jeffrey, M. ,  BREHMER, Geoffrey, E. ,  BROWN, Glen, W. ,  CABLER, Carlin, Dru ,  FEEMSTER, Ryan ,  GUERCIO, David ,  GULICK, Dale, E. ,  HOGAN, Michael ,  LINZ, Alfredo, R. ,  NORRIS, David ,  SCHNIZLEIN, Paul, G. ,  SOQUES, Martin, P. ,  SPAK, Michael, E. ,  SUGGS, David, N. ,  TOROK, Alan, T.

IPC: G06F00/00

CPC classification number: H03K23/68 ,  F02B2075/027 ,  G06F3/162 ,  G10H1/0066 ,  G10H1/125 ,  G10H7/002 ,  G10H2220/315 ,  G10H2230/035 ,  G10H2240/311 ,  G10H2250/115 ,  G10H2250/191 ,  G10H2250/545 ,  G10H2250/571 ,  G10H2250/605 ,  G10H2250/611

Abstract: A monolithic integrated circuit for providing enhanced audio performance in personal computers is disclosed. The monolithic circuit includes a wavetable synthesizer; a full function stereo coding and decoding circuit (CODEC) including analog-to-digital and digital-to-analog data conversion; data compression, and mixing and muxing of analog signals; a local memory control module for interfacing with external memory; a game-MIDI port module; a system bus interface; and a control module for compatibility and circuit control functions.

Abstract translation: 公开了一种用于在个人计算机中提供增强的音频性能的单片集成电路。 单片电路包括波形合成器; 全功能立体声编解码电路（CODEC），包括模数转换和数模转换; 数据压缩，模拟信号的混合和复用; 用于与外部存储器接口的本地存储器控制模块; 一个游戏MIDI口模块; 一个系统总线接口; 以及用于兼容性和电路控制功能的控制模块。

公开(公告)号：WO2007044133A1

公开(公告)日：2007-04-19

申请号：PCT/US2006/032920

申请日：2006-08-23

Applicant: ADVANCED MICRO DEVICES, INC. ,  LIU, Huining ,  HEWITT, Larry, D.

Inventor： LIU, Huining ,  HEWITT, Larry, D.

IPC: G01K7/20

CPC classification number: G01K7/203

Abstract: A method and apparatus for temperature sensing in an IC. The IC (10) includes a plurality of remote temperature sensors (40) each coupled to a control logic unit (20). The plurality of remote temperature sensors may be distributed throughout the integrated circuit. The integrated circuit includes a reference unit (30) coupled to provide a reference temperature to the control logic unit and a reference sensor (35) coupled to provide a signal having a reference frequency to the control logic unit. The reference unit and the reference sensor are located near each other. The control logic unit is configured to correlate the reference frequency received from the reference sensor with the reference temperature received from the reference unit. The control logic unit is further configured to determine the temperature of each of the remote temperature sensors based on this correlation, and also configured to determine the maximum temperature of all of the temperature sensors.

Abstract translation: 一种用于IC中温度感测的方法和装置。 IC（10）包括多个远程温度传感器（40），每个远程温度传感器耦合到控制逻辑单元（20）。 多个远程温度传感器可以分布在整个集成电路中。 集成电路包括耦合以向控制逻辑单元提供参考温度的参考单元（30）和耦合以向控制逻辑单元提供具有参考频率的信号的参考传感器（35）。 参考单元和参考传感器彼此靠近。 控制逻辑单元被配置为将从参考传感器接收的参考频率与从参考单元接收的参考温度相关联。 控制逻辑单元还被配置为基于该相关性来确定每个远程温度传感器的温度，并且还被配置为确定所有温度传感器的最高温度。

公开(公告)号：WO2003034240A1

公开(公告)日：2003-04-24

申请号：PCT/US2002/026884

申请日：2002-08-22

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ASKAR, Tahsin ,  HEWITT, Larry, D. ,  CHAMBERS, Eric, G.

IPC: G06F13/12

CPC classification number: G06F13/128

Abstract: A peripheral interface circuit (350) for an I/O node of a computer system. A peripheral interface circuit for an input/output node of a computer system includes a first buffer circuit (390), a second buffer circuit (5300) and a bus interface circuit (490). The first buffer circuit receives packet commands and may include a first plurality of buffers each corresponding to a respective virtual channel of a plurality of virtual channels. The second buffer circuit is coupled to receive packet commands from the bus interface circuit and may include a second plurality of buffers each corresponding to a respective virtual channel of the plurality of virtual channels. The bus interface circuit may be configured to translate selected packet commands stored in the first buffer circuit into commands suitable for transmission on a peripheral bus (560).

Abstract translation: 一种用于计算机系统的I / O节点的外围接口电路（350）。 用于计算机系统的输入/输出节点的外围接口电路包括第一缓冲电路（390），第二缓冲电路（5300）和总线接口电路（490）。 第一缓冲电路接收分组命令，并且可以包括每个对应于多个虚拟通道的相应虚拟通道的第一多个缓冲器。 第二缓冲电路被耦合以从总线接口电路接收分组命令，并且可以包括每个对应于多个虚拟通道中的相应虚拟通道的第二多个缓冲器。 总线接口电路可以被配置为将存储在第一缓冲器电路中的选择的分组命令转换成适合于在外围总线（560）上传输的命令。

公开(公告)号：WO2019040510A1

公开(公告)日：2019-02-28

申请号：PCT/US2018/047350

申请日：2018-08-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： GIBNEY, Thomas J. ,  HEWITT, Larry, D. ,  BOUVIER, Daniel, L.

IPC: H02M1/00 ,  G06F1/26

Abstract: The described embodiments include an apparatus that controls voltages for an integrated circuit chip having a set of circuits. The apparatus includes a switching voltage regulator separate from the integrated circuit chip and two or more low dropout (LDO) regulators fabricated on the integrated circuit chip. During operation, the switching voltage regulator provides an output voltage that is received as an input voltage by each of the two or more LDO regulators, and each of the two or more LDO regulators provides a local output voltage, each local output voltage received as a local input voltage by a different subset of circuits in the set of circuits

公开(公告)号：WO2004102403A2

公开(公告)日：2004-11-25

申请号：PCT/US2004/014441

申请日：2004-05-10

Applicant: ADVANCED MICRO DEVICES, INC. ,  POLZIN, R., Stephen ,  WEBER, Frederick, D. ,  TALBOT, Gerald, R. ,  HEWITT, Larry, D. ,  REEVES, Richard, W. ,  PATEL, Shwetal, A. ,  LA FETRA, Ross, V. ,  GULICK, Dale, E. ,  HUMMEL, Mark, D. ,  MIRANDA, Paul, C.

Inventor： POLZIN, R., Stephen ,  WEBER, Frederick, D. ,  TALBOT, Gerald, R. ,  HEWITT, Larry, D. ,  REEVES, Richard, W. ,  PATEL, Shwetal, A. ,  LA FETRA, Ross, V. ,  GULICK, Dale, E. ,  HUMMEL, Mark, D. ,  MIRANDA, Paul, C.

IPC: G06F13/16

CPC classification number: G06F13/4243 ,  G06F12/0215 ,  G06F12/0862 ,  G06F13/1626 ,  G06F2212/6022

Abstract: A system (50) including a host (100) coupled to a serially connected chain of memory modules (150A-B). In one embodiment, each of the memory modules includes a memory control hub (160) for controlling access to a plurality of memory chips (261) on the memory module. The memory modules are coupled serially in a chain to the host via a plurality of memory links (110). Each memory link may include an uplink (211) for conveying transactions toward the host and a downlink (212) for conveying transactions originating at the host to a next memory module in the chain. The uplink and the downlink may convey transactions using packets that include control and configuration packets and memory access packets. The memory control hub may convey a transaction received on a first downlink of a first memory link on a second downlink of a second memory link independent of decoding the transaction.

Abstract translation: 一种系统（50），包括耦合到串行连接的存储器模块链（150A-B）的主机（100）。 在一个实施例中，每个存储器模块包括用于控制对存储器模块上的多个存储器芯片（261）的访问的存储器控​​制集线器（160）。 存储器模块通过多个存储器链路（110）以链式串行耦合到主机。 每个存储器链路可以包括用于向主机传送事务的上行链路（211）和用于将在主机处发起的事务传送到链路中的下一个存储器模块的下行链路（212）。 上行链路和下行链路可以使用包括控制和配置分组和存储器访问分组的分组来传送事务。 存储器控制集线器可以在第二存储器链路的第二下行链路上传送在第一存储器链路的第一下行链路上接收的事务，而与解码事务无关。

公开(公告)号：WO2003034239A1

公开(公告)日：2003-04-24

申请号：PCT/US2002/025278

申请日：2002-08-09

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ENNIS, Stephen, C. ,  HEWITT, Larry, D.

IPC: G06F13/12

CPC classification number: G06F13/128

Abstract: A computer system I/O node. An input/output (20, 30, 40) for a computer system includes a first receiver unit (110) configured to receive a first command on a first communication path and a first transmitter unit (140) coupled to transmit a first corresponding command that corresponds to the first command on a second communication path. The input/output node also includes a second receiver unit (120) configured to receive a second command on a third communication path and a second transmitter (130) unit coupled to transmit a second corresponding command that corresponds to the second command on a fourth communication path. Further, the input/output node includes a bridge unit (150) coupled to receive selected commands from the first receiver and the second receiver and configured to transmit commands corresponding to the selected commands upon a peripheral bus (152).

Abstract translation: 计算机系统I / O节点。 用于计算机系统的输入/输出（20,30,40）包括被配置为在第一通信路径上接收第一命令的第一接收器单元（110）和耦合以发送第一对应命令的第一发送器单元（140） 对应于第二通信路径上的第一命令。 输入/输出节点还包括被配置为在第三通信路径上接收第二命令的第二接收器单元（120）和耦合以在第四通信上发送对应于第二命令的第二对应命令的第二发送器（130）单元 路径。 此外，输入/输出节点包括桥接单元（150），桥单元（150）被耦合以从第一接收器和第二接收器接收所选择的命令，并且被配置为在外围总线（152）上传送与所选择的命令相对应的命令。

公开(公告)号：EP1008049A1

公开(公告)日：2000-06-14

申请号：EP97948495.3

申请日：1997-11-20

Applicant: Advanced Micro Devices, Inc.

Inventor： HEWITT, Larry, D.

IPC: G06F11/30 ,  G06F13/42

CPC classification number: G06F11/3027 ,  G06F11/3079 ,  G06F13/423 ,  G06F2201/81 ,  G06F2201/88

Abstract: An arrangement for monitoring clock frequency variations on a peripheral bus is provided to improve operations of the peripheral device despite changes in the clock frequency. In one aspect of the arrangement, a processing unit is coupled to a host bus which in turn is coupled to a peripheral bus which is coupled to a peripheral device. A monitoring arrangement is provided which detects a change in the clock frequency of the peripheral bus and determines if the frequency change exceeds a threshold associated with the peripheral device. If the threshold is exceeded, the peripheral device is informed that the clock frequency of the peripheral bus has changed. A peripheral device operating a different operating levels may use the information from the monitoring arrangement to alter the operating level of the peripheral device to conform to the new bus clock frequency.

公开(公告)号：EP1436709B1

公开(公告)日：2006-04-26

申请号：EP02801621.0

申请日：2002-08-22

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ASKAR, Tahsin ,  HEWITT, Larry, D. ,  CHAMBERS, Eric, G.

IPC: G06F13/12

CPC classification number: G06F13/128

Abstract: A peripheral interface circuit (350) for an I/O node of a computer system. A peripheral interface circuit for an input/output node of a computer system includes a first buffer circuit (390), a second buffer circuit (5300) and a bus interface circuit (490). The first buffer circuit receives packet commands and may include a first plurality of buffers each corresponding to a respective virtual channel of a plurality of virtual channels. The second buffer circuit is coupled to receive packet commands from the bus interface circuit and may include a second plurality of buffers each corresponding to a respective virtual channel of the plurality of virtual channels. The bus interface circuit may be configured to translate selected packet commands stored in the first buffer circuit into commands suitable for transmission on a peripheral bus (560).