公开(公告)号：WO2002078060A2

公开(公告)日：2002-10-03

申请号：PCT/US2001/049825

申请日：2001-12-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： YANG, Kai ,  ERB, Darrell, M. ,  WANG, Fei

IPC: H01L21/00

CPC classification number: H01L21/76831 ,  H01L21/76802 ,  H01L21/76807 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Damascene processing is implemented with dielectric barrier films (50, 90, 91) for improved step coverage and reduced contact resistance. Embodiments include the use of two different dielectric films (50, 31) to avoid misalignment problems. Embodiments further include dual damascene (100A, 100B) processing using Cu metallization (100).

Abstract translation: 用电介质阻挡膜（50,90,91）实现镶嵌加工，以改善台阶覆盖和降低的接触电阻。 实施例包括使用两种不同的介电膜（50,31）来避免不对准问题。 实施例还包括使用Cu金属化（100）的双镶嵌（100A，100B）处理。

公开(公告)号：WO2003052816A1

公开(公告)日：2003-06-26

申请号：PCT/US2002/039736

申请日：2002-12-11

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADEM, Ercam ,  ERB, Darrell, M.

IPC: H01L21/768

CPC classification number: H01L21/76819 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76885

Abstract: A nonporous sacrificial layer (30) is used to form conductive elements (34) such as vias or interconnects in an inlay process, resulting in smooth walled structures of the inlaid vias or interconnects and smooth walled structures of any surrounding layers such as barrier layers. After formation of the smooth walled conductive elements, the sacrificial layer (30) is removed and replaced with a porous dielectric (40), resulting in desirable porous low-k dielectric structures integrated with the smooth walled conductive elements and barrier materials.

Abstract translation: 无孔牺牲层（30）用于在嵌入式工艺中形成诸如通路或互连件的导电元件（34），从而导致镶嵌过孔或互连件的平滑壁结构以及诸如阻挡层的任何周围层的平滑壁结构。 在形成光滑的壁导电元件之后，去除牺牲层（30）并用多孔电介质（40）代替，从而产生与光滑壁导电元件和阻挡材料一体化的期望的多孔低k电介质结构。

公开(公告)号：WO2003052794A3

公开(公告)日：2003-06-26

申请号：PCT/US2002/039738

申请日：2002-12-11

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： AVANZINO, Steven, C. ,  ERB, Darrell, M. ,  WANG, Fei ,  LOPATIN, Sergey

IPC: H01L21/768

Abstract: A precursor (30) of a low-k porous dielectric is applied to an integrated circuit substrate (20). The precursor comprises a host thermosetting material and a porogen. Crosslinking of at least some of the first host thermosetting material is produced to form a low-k dielectric matrix without decomposing all of the porogen. This leaves a solid nonporous layer of the low-k dielectric matrix. Conductive elements (54) are then inlaid in the low-k dielectric matrix. After the conductive elements are formed, remaining porogen is decomposed to leave a porous low-k dielectric layer (58, 60). The resulting conductive elements are smooth walled.

公开(公告)号：WO2003052794A2

公开(公告)日：2003-06-26

申请号：PCT/US2002/039738

申请日：2002-12-11

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： AVANZINO, Steven, C. ,  ERB, Darrell, M. ,  WANG, Fei ,  LOPATIN, Sergey

IPC: H01L

CPC classification number: H01L21/02118 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/31695 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/7682 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A precursor (30) of a low-k porous dielectric is applied to an integrated circuit substrate (20). The precursor comprises a host thermosetting material and a porogen. Crosslinking of at least some of the first host thermosetting material is produced to form a low-k dielectric matrix (31) without decomposing all of the porogen. This leaves a solid nonporous layer of the low-k dielectric matrix. Conductive elements (36) are then inlaid in the low-k dielectric matrix. After the conductive elements are formed, remaining porogen is decomposed to leave a porous low-k dielectric layer (42). The resulting conductive elements are smooth walled.

Abstract translation: 将低k多孔电介质的前体（30）施加到集成电路基板（20）。 前体包括主体热固性材料和致孔剂。 产生至少一些第一主体热固性材料的交联以形成低k电介质基质（31）而不分解所有的致孔剂。 这留下了低k电介质矩阵的固体无孔层。 然后将导电元件（36）镶嵌在低k电介质矩阵中。 在形成导电元件之后，剩余的致孔剂被分解以留下多孔的低k电介质层（42）。 所得到的导电元件是平滑的。

公开(公告)号：EP1374300A2

公开(公告)日：2004-01-02

申请号：EP01998081.2

申请日：2001-12-19

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： YANG, Kai ,  ERB, Darrell, M. ,  WANG, Fei

IPC: H01L21/768

CPC classification number: H01L21/76831 ,  H01L21/76802 ,  H01L21/76807 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Damascene processing is implemented with dielectric barrier films (50, 90, 91) for improved step coverage and reduced contact resistance. Embodiments include the use of two different dielectric films (50, 31) to avoid misalignment problems. Embodiments further include dual damascene (100A, 100B) processing using Cu metallization (100).